drm/i915/cnl: Drop all workarounds

All of the Cannon Lake hardware that came out had graphics fused off,
and our userspace drivers have already dropped their support for the
platform; CNL-specific code in i915 that isn't inherited by subsequent
platforms is effectively dead code.  Let's remove all of the
CNL-specific workarounds as a quick and easy first step.

References: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210713193635.3390052-12-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 78fd58c..e9dc2d5 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -514,35 +514,6 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
                     GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 }
 
-static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
-                                    struct i915_wa_list *wal)
-{
-       /* WaForceContextSaveRestoreNonCoherent:cnl */
-       wa_masked_en(wal, CNL_HDC_CHICKEN0,
-                    HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-
-       /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
-       wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
-                    GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-
-       /* WaPushConstantDereferenceHoldDisable:cnl */
-       wa_masked_en(wal, GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
-
-       /* FtrEnableFastAnisoL1BankingFix:cnl */
-       wa_masked_en(wal, HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
-
-       /* WaDisable3DMidCmdPreemption:cnl */
-       wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
-
-       /* WaDisableGPGPUMidCmdPreemption:cnl */
-       wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
-                           GEN9_PREEMPT_GPGPU_LEVEL_MASK,
-                           GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
-
-       /* WaDisableEarlyEOT:cnl */
-       wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
-}
-
 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
                                     struct i915_wa_list *wal)
 {
@@ -703,8 +674,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
                gen12_ctx_workarounds_init(engine, wal);
        else if (GRAPHICS_VER(i915) == 11)
                icl_ctx_workarounds_init(engine, wal);
-       else if (IS_CANNONLAKE(i915))
-               cnl_ctx_workarounds_init(engine, wal);
        else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
                cfl_ctx_workarounds_init(engine, wal);
        else if (IS_GEMINILAKE(i915))
@@ -1016,17 +985,6 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 }
 
 static void
-cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
-{
-       wa_init_mcr(i915, wal);
-
-       /* WaInPlaceDecompressionHang:cnl */
-       wa_write_or(wal,
-                   GEN9_GAMT_ECO_REG_RW_IA,
-                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-}
-
-static void
 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
        wa_init_mcr(i915, wal);
@@ -1175,8 +1133,6 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
                gen12_gt_workarounds_init(i915, wal);
        else if (GRAPHICS_VER(i915) == 11)
                icl_gt_workarounds_init(i915, wal);
-       else if (IS_CANNONLAKE(i915))
-               cnl_gt_workarounds_init(i915, wal);
        else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
                cfl_gt_workarounds_init(i915, wal);
        else if (IS_GEMINILAKE(i915))
@@ -1438,17 +1394,6 @@ static void cml_whitelist_build(struct intel_engine_cs *engine)
        cfl_whitelist_build(engine);
 }
 
-static void cnl_whitelist_build(struct intel_engine_cs *engine)
-{
-       struct i915_wa_list *w = &engine->whitelist;
-
-       if (engine->class != RENDER_CLASS)
-               return;
-
-       /* WaEnablePreemptionGranularityControlByUMD:cnl */
-       whitelist_reg(w, GEN8_CS_CHICKEN1);
-}
-
 static void icl_whitelist_build(struct intel_engine_cs *engine)
 {
        struct i915_wa_list *w = &engine->whitelist;
@@ -1562,8 +1507,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
                tgl_whitelist_build(engine);
        else if (GRAPHICS_VER(i915) == 11)
                icl_whitelist_build(engine);
-       else if (IS_CANNONLAKE(i915))
-               cnl_whitelist_build(engine);
        else if (IS_COMETLAKE(i915))
                cml_whitelist_build(engine);
        else if (IS_COFFEELAKE(i915))

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d93159f..5e640e2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1454,13 +1454,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
        (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 
-#define CNL_REVID_A0           0x0
-#define CNL_REVID_B0           0x1
-#define CNL_REVID_C0           0x2
-
-#define IS_CNL_REVID(p, since, until) \
-       (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
-
 #define IS_ICL_GT_STEP(p, since, until) \
        (IS_ICELAKE(p) && IS_GT_STEP(p, since, until))