ARM: EXYNOS: Add IO mapping for non-secure SYSRAM.
authorTomasz Figa <t.figa@samsung.com>
Tue, 11 Dec 2012 04:58:43 +0000 (13:58 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Mon, 8 Apr 2013 16:52:30 +0000 (01:52 +0900)
On TrustZone-enabled boards the non-secure SYSRAM is used for secondary
CPU bring-up, so add a mapping for it.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-exynos/common.c
arch/arm/mach-exynos/include/mach/map.h
arch/arm/plat-samsung/include/plat/map-s5p.h

index 02e35abd136b4ae39aba1c70a7068715cfdab0c8..b2bb2b70832bee2616497505269a2ebfbe6da9b0 100644 (file)
@@ -232,6 +232,33 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
        },
 };
 
+static struct map_desc exynos4210_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc exynos4x12_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc exynos5250_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
 static struct map_desc exynos5_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -360,6 +387,11 @@ static void __init exynos4_map_io(void)
        else
                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 
+       if (soc_is_exynos4210())
+               iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+       if (soc_is_exynos4212() || soc_is_exynos4412())
+               iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
+
        /* initialize device information early */
        exynos4_default_sdhci0();
        exynos4_default_sdhci1();
@@ -392,6 +424,9 @@ static void __init exynos4_map_io(void)
 static void __init exynos5_map_io(void)
 {
        iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+       if (soc_is_exynos5250())
+               iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 }
 
 static void __init exynos5440_map_io(void)
index 7f99b7b187d66e6e247ee534b15000a392cb63ee..99e0a79f3b1f622a48bf4421a3d64776183de402 100644 (file)
@@ -26,6 +26,9 @@
 #define EXYNOS4_PA_SYSRAM0             0x02025000
 #define EXYNOS4_PA_SYSRAM1             0x02020000
 #define EXYNOS5_PA_SYSRAM              0x02020000
+#define EXYNOS4210_PA_SYSRAM_NS                0x0203F000
+#define EXYNOS4x12_PA_SYSRAM_NS                0x0204F000
+#define EXYNOS5250_PA_SYSRAM_NS                0x0204F000
 
 #define EXYNOS4_PA_FIMC0               0x11800000
 #define EXYNOS4_PA_FIMC1               0x11810000
index c2d7bdae589106d5928e3b36142cb4348bfc67d3..c18678610bc0ad952eba51726ef9f3d198caf44c 100644 (file)
@@ -22,6 +22,7 @@
 #define S5P_VA_GPIO3           S3C_ADDR(0x02280000)
 
 #define S5P_VA_SYSRAM          S3C_ADDR(0x02400000)
+#define S5P_VA_SYSRAM_NS       S3C_ADDR(0x02410000)
 #define S5P_VA_DMC0            S3C_ADDR(0x02440000)
 #define S5P_VA_DMC1            S3C_ADDR(0x02480000)
 #define S5P_VA_SROMC           S3C_ADDR(0x024C0000)