ASoC: cs42l42: Ensure a reset pulse meets minimum pulse width.

The CS42L42 can accept very short reset pulses of a few microseconds
but there's no reason to force a very short pulse.
Allow a wide range for the usleep_range() so it can be relaxed about
the choice of timing source.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230913150012.604775-2-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index a0de0329406a1ff2ea3dc8a29f4ec510335553dd..56d2857a4f01c7641a753662090f0b080b21b855 100644 (file)
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -2320,6 +2320,10 @@ int cs42l42_common_probe(struct cs42l42_private *cs42l42,
 
        if (cs42l42->reset_gpio) {
                dev_dbg(cs42l42->dev, "Found reset GPIO\n");
+
+               /* Ensure minimum reset pulse width */
+               usleep_range(10, 500);
+
                gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
        }
        usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);