clk: renesas: Add r8a7742 CPG Core Clock Definitions

Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
Manual.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/include/dt-bindings/clock/r8a7742-cpg-mssr.h b/include/dt-bindings/clock/r8a7742-cpg-mssr.h
new file mode 100644 (file)
index 0000000..e68191c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7742-cpg-mssr.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7742 CPG Core Clocks */
+#define R8A7742_CLK_Z          0
+#define R8A7742_CLK_Z2         1
+#define R8A7742_CLK_ZG         2
+#define R8A7742_CLK_ZTR                3
+#define R8A7742_CLK_ZTRD2      4
+#define R8A7742_CLK_ZT         5
+#define R8A7742_CLK_ZX         6
+#define R8A7742_CLK_ZS         7
+#define R8A7742_CLK_HP         8
+#define R8A7742_CLK_B          9
+#define R8A7742_CLK_LB         10
+#define R8A7742_CLK_P          11
+#define R8A7742_CLK_CL         12
+#define R8A7742_CLK_M2         13
+#define R8A7742_CLK_ZB3                14
+#define R8A7742_CLK_ZB3D2      15
+#define R8A7742_CLK_DDR                16
+#define R8A7742_CLK_SDH                17
+#define R8A7742_CLK_SD0                18
+#define R8A7742_CLK_SD1                19
+#define R8A7742_CLK_SD2                20
+#define R8A7742_CLK_SD3                21
+#define R8A7742_CLK_MMC0       22
+#define R8A7742_CLK_MMC1       23
+#define R8A7742_CLK_MP         24
+#define R8A7742_CLK_QSPI       25
+#define R8A7742_CLK_CP         26
+#define R8A7742_CLK_RCAN       27
+#define R8A7742_CLK_R          28
+#define R8A7742_CLK_OSC                29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */