/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
- Copyright (C) 1991,92,94,95,96,97,98,99,2000,2001 Free Software Foundation, Inc.
+ Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+ Free Software Foundation, Inc.
+
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
is rounded towards 0.
5) count_leading_zeros(count, x) counts the number of zero-bits from the
- msb to the first non-zero bit in the UWtype X. This is the number of
+ msb to the first nonzero bit in the UWtype X. This is the number of
steps X needs to be shifted left to set the msb. Undefined for X == 0,
unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
#define __AND_CLOBBER_CC , "cc"
#endif /* __GNUC__ < 2 */
-#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("add %1,%4,%5\n" \
- "addc %0,%2,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%r" ((USItype) (ah)), \
- "rI" ((USItype) (bh)), \
- "%r" ((USItype) (al)), \
- "rI" ((USItype) (bl)))
-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("sub %1,%4,%5\n" \
- "subc %0,%2,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (ah)), \
- "rI" ((USItype) (bh)), \
- "r" ((USItype) (al)), \
- "rI" ((USItype) (bl)))
-#define umul_ppmm(xh, xl, m0, m1) \
- do { \
- USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("multiplu %0,%1,%2" \
- : "=r" ((USItype) (xl)) \
- : "r" (__m0), \
- "r" (__m1)); \
- __asm__ ("multmu %0,%1,%2" \
- : "=r" ((USItype) (xh)) \
- : "r" (__m0), \
- "r" (__m1)); \
- } while (0)
-#define udiv_qrnnd(q, r, n1, n0, d) \
- __asm__ ("dividu %0,%3,%4" \
- : "=r" ((USItype) (q)), \
- "=q" ((USItype) (r)) \
- : "1" ((USItype) (n1)), \
- "r" ((USItype) (n0)), \
- "r" ((USItype) (d)))
-#define count_leading_zeros(count, x) \
- __asm__ ("clz %0,%1" \
- : "=r" ((USItype) (count)) \
- : "r" ((USItype) (x)))
-#define COUNT_LEADING_ZEROS_0 32
-#endif /* __a29k__ */
-
#if defined (__alpha) && W_TYPE_SIZE == 64
#define umul_ppmm(ph, pl, m0, m1) \
do { \
(q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
(r) = __r; \
} while (0)
-extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
+extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype));
#define UDIV_TIME 220
#endif /* LONGLONG_STANDALONE */
+#ifdef __alpha_cix__
+#define count_leading_zeros(COUNT,X) \
+ __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
+#define count_trailing_zeros(COUNT,X) \
+ __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
+#define COUNT_LEADING_ZEROS_0 64
+#else
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(COUNT,X) \
+ do { \
+ UDItype __xr = (X), __t, __a; \
+ __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \
+ __a = __clz_tab[__t ^ 0xff] - 1; \
+ __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \
+ (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
+ } while (0)
+#define count_trailing_zeros(COUNT,X) \
+ do { \
+ UDItype __xr = (X), __t, __a; \
+ __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \
+ __t = ~__t & -~__t; \
+ __a = ((__t & 0xCC) != 0) * 2; \
+ __a += ((__t & 0xF0) != 0) * 4; \
+ __a += ((__t & 0xAA) != 0); \
+ __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \
+ __a <<= 3; \
+ __t &= -__t; \
+ __a += ((__t & 0xCC) != 0) * 2; \
+ __a += ((__t & 0xF0) != 0) * 4; \
+ __a += ((__t & 0xAA) != 0); \
+ (COUNT) = __a; \
+ } while (0)
+#endif /* __alpha_cix__ */
#endif /* __alpha */
#if defined (__arc__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("add.f %1, %4, %5\n" \
- "adc %0, %2, %3" \
+ __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \
"%r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("sub.f %1, %4, %5\n" \
- "sbc %0, %2, %3" \
+ __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
-/* Call libgcc1 routine. */
+/* Call libgcc routine. */
#define umul_ppmm(w1, w0, u, v) \
do { \
- DIunion __w; \
+ DWunion __w; \
__w.ll = __umulsidi3 (u, v); \
w1 = __w.s.high; \
w0 = __w.s.low; \
#if defined (__arm__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("adds %1, %4, %5\n" \
- "adc %0, %2, %3" \
+ __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \
"%r" ((USItype) (al)), \
"rI" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subs %1, %4, %5\n" \
- "sbc %0, %2, %3" \
+ __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \
#define umul_ppmm(xh, xl, a, b) \
{register USItype __t0, __t1, __t2; \
__asm__ ("%@ Inlined umul_ppmm\n" \
- "mov %2, %5, lsr #16\n" \
- "mov %0, %6, lsr #16\n" \
- "bic %3, %5, %2, lsl #16\n" \
- "bic %4, %6, %0, lsl #16\n" \
- "mul %1, %3, %4\n" \
- "mul %4, %2, %4\n" \
- "mul %3, %0, %3\n" \
- "mul %0, %2, %0\n" \
- "adds %3, %4, %3\n" \
- "addcs %0, %0, #65536\n" \
- "adds %1, %1, %3, lsl #16\n" \
- "adc %0, %0, %3, lsr #16" \
+ " mov %2, %5, lsr #16\n" \
+ " mov %0, %6, lsr #16\n" \
+ " bic %3, %5, %2, lsl #16\n" \
+ " bic %4, %6, %0, lsl #16\n" \
+ " mul %1, %3, %4\n" \
+ " mul %4, %2, %4\n" \
+ " mul %3, %0, %3\n" \
+ " mul %0, %2, %0\n" \
+ " adds %3, %4, %3\n" \
+ " addcs %0, %0, #65536\n" \
+ " adds %1, %1, %3, lsl #16\n" \
+ " adc %0, %0, %3, lsr #16" \
: "=&r" ((USItype) (xh)), \
"=r" ((USItype) (xl)), \
"=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
#define UDIV_TIME 100
#endif /* __arm__ */
-#if defined (__clipper__) && W_TYPE_SIZE == 32
-#define umul_ppmm(w1, w0, u, v) \
- ({union {UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- __asm__ ("mulwux %2,%0" \
- : "=r" (__xx.__ll) \
- : "%0" ((USItype) (u)), \
- "r" ((USItype) (v))); \
- (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
-#define smul_ppmm(w1, w0, u, v) \
- ({union {DItype __ll; \
- struct {SItype __l, __h;} __i; \
- } __xx; \
- __asm__ ("mulwx %2,%0" \
- : "=r" (__xx.__ll) \
- : "%0" ((SItype) (u)), \
- "r" ((SItype) (v))); \
- (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
-#define __umulsidi3(u, v) \
- ({UDItype __w; \
- __asm__ ("mulwux %2,%0" \
- : "=r" (__w) \
- : "%0" ((USItype) (u)), \
- "r" ((USItype) (v))); \
- __w; })
-#endif /* __clipper__ */
-
-#if defined (__gmicro__) && W_TYPE_SIZE == 32
-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("add.w %5,%1\n" \
- "addx %3,%0" \
- : "=g" ((USItype) (sh)), \
- "=&g" ((USItype) (sl)) \
- : "%0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "%1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("sub.w %5,%1\n" \
- "subx %3,%0" \
- : "=g" ((USItype) (sh)), \
- "=&g" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
-#define umul_ppmm(ph, pl, m0, m1) \
- __asm__ ("mulx %3,%0,%1" \
- : "=g" ((USItype) (ph)), \
- "=r" ((USItype) (pl)) \
- : "%0" ((USItype) (m0)), \
- "g" ((USItype) (m1)))
-#define udiv_qrnnd(q, r, nh, nl, d) \
- __asm__ ("divx %4,%0,%1" \
- : "=g" ((USItype) (q)), \
- "=r" ((USItype) (r)) \
- : "1" ((USItype) (nh)), \
- "0" ((USItype) (nl)), \
- "g" ((USItype) (d)))
-#define count_leading_zeros(count, x) \
- __asm__ ("bsch/1 %1,%0" \
- : "=g" (count) \
- : "g" ((USItype) (x)), \
- "0" ((USItype) 0))
-#endif
-
#if defined (__hppa) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("add %4,%5,%1\n" \
- "addc %2,%3,%0" \
+ __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%rM" ((USItype) (ah)), \
"%rM" ((USItype) (al)), \
"rM" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("sub %4,%5,%1\n" \
- "subb %2,%3,%0" \
+ __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "rM" ((USItype) (ah)), \
#endif
#define UDIV_TIME 40
#define count_leading_zeros(count, x) \
- do { \
- USItype __tmp; \
- __asm__ ( \
- "ldi 1,%0\n" \
- "extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
- "extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
- "ldo 16(%0),%0 ; Yes. Perform add.\n" \
- "extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
- "extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
- "ldo 8(%0),%0 ; Yes. Perform add.\n" \
- "extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
- "extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
- "ldo 4(%0),%0 ; Yes. Perform add.\n" \
- "extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
- "extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
- "ldo 2(%0),%0 ; Yes. Perform add.\n" \
- "extru %1,30,1,%1 ; Extract bit 1.\n" \
- "sub %0,%1,%0 ; Subtract it." \
- : "=r" (count), "=r" (__tmp) : "1" (x)); \
+ do { \
+ USItype __tmp; \
+ __asm__ ( \
+ "ldi 1,%0\n" \
+" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
+" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
+" ldo 16(%0),%0 ; Yes. Perform add.\n" \
+" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
+" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
+" ldo 8(%0),%0 ; Yes. Perform add.\n" \
+" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
+" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
+" ldo 4(%0),%0 ; Yes. Perform add.\n" \
+" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
+" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
+" ldo 2(%0),%0 ; Yes. Perform add.\n" \
+" extru %1,30,1,%1 ; Extract bit 1.\n" \
+" sub %0,%1,%0 ; Subtract it.\n" \
+ : "=r" (count), "=r" (__tmp) : "1" (x)); \
} while (0)
#endif
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addl %5,%1\n" \
- "adcl %3,%0" \
+ __asm__ ("addl %5,%1\n\tadcl %3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subl %5,%1\n" \
- "sbbl %3,%0" \
+ __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"=d" ((USItype) (w1)) \
: "%0" ((USItype) (u)), \
"rm" ((USItype) (v)))
-#define udiv_qrnnd(q, r, n1, n0, d) \
+#define udiv_qrnnd(q, r, n1, n0, dv) \
__asm__ ("divl %4" \
: "=a" ((USItype) (q)), \
"=d" ((USItype) (r)) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
- "rm" ((USItype) (d)))
+ "rm" ((USItype) (dv)))
#define count_leading_zeros(count, x) \
do { \
USItype __cbtmp; \
#define UDIV_TIME 40
#endif /* 80x86 */
-#if defined (__i860__) && W_TYPE_SIZE == 32
-#if 0
-/* Make sure these patterns really improve the code before
- switching them on. */
-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- do { \
- union \
- { \
- DItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __a, __b, __s; \
- __a.__i.__l = (al); \
- __a.__i.__h = (ah); \
- __b.__i.__l = (bl); \
- __b.__i.__h = (bh); \
- __asm__ ("fiadd.dd %1,%2,%0" \
- : "=f" (__s.__ll) \
- : "%f" (__a.__ll), "f" (__b.__ll)); \
- (sh) = __s.__i.__h; \
- (sl) = __s.__i.__l; \
- } while (0)
-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- do { \
- union \
- { \
- DItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __a, __b, __s; \
- __a.__i.__l = (al); \
- __a.__i.__h = (ah); \
- __b.__i.__l = (bl); \
- __b.__i.__h = (bh); \
- __asm__ ("fisub.dd %1,%2,%0" \
- : "=f" (__s.__ll) \
- : "%f" (__a.__ll), "f" (__b.__ll)); \
- (sh) = __s.__i.__h; \
- (sl) = __s.__i.__l; \
- } while (0)
-#endif
-#endif /* __i860__ */
-
#if defined (__i960__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
#if defined (__M32R__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \
- __asm__ ("cmp %0,%0\n" \
- "addx %%5,%1\n" \
- "addx %%3,%0" \
+ __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
: "cbit")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \
- __asm__ ("cmp %0,%0\n" \
- "subx %5,%1\n" \
- "subx %3,%0" \
+ __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
#if defined (__mc68000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("add%.l %5,%1\n" \
- "addx%.l %3,%0" \
+ __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
: "=d" ((USItype) (sh)), \
"=&d" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("sub%.l %5,%1\n" \
- "subx%.l %3,%0" \
+ __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
: "=d" ((USItype) (sh)), \
"=&d" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"1" ((USItype) (al)), \
"g" ((USItype) (bl)))
-/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
+/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
#if defined (__mc68020__) || defined(mc68020) \
|| defined(__mc68030__) || defined(mc68030) \
|| defined(__mc68040__) || defined(mc68040) \
- || defined(__mcpu32__) || defined(mcpu32) \
- || defined(__NeXT__)
+ || defined(__mcpu32__) || defined(mcpu32)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
: "=d" ((USItype) (w0)), \
/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
#define umul_ppmm(xh, xl, a, b) \
__asm__ ("| Inlined umul_ppmm\n" \
-" move%.l %2,%/d0\n" \
-" move%.l %3,%/d1\n" \
-" move%.l %/d0,%/d2\n" \
-" swap %/d0\n" \
-" move%.l %/d1,%/d3\n" \
-" swap %/d1\n" \
-" move%.w %/d2,%/d4\n" \
-" mulu %/d3,%/d4\n" \
-" mulu %/d1,%/d2\n" \
-" mulu %/d0,%/d3\n" \
-" mulu %/d0,%/d1\n" \
-" move%.l %/d4,%/d0\n" \
-" eor%.w %/d0,%/d0\n" \
-" swap %/d0\n" \
-" add%.l %/d0,%/d2\n" \
-" add%.l %/d3,%/d2\n" \
-" jcc 1f\n" \
-" add%.l %#65536,%/d1\n" \
-"1: swap %/d2\n" \
-" moveq %#0,%/d0\n" \
-" move%.w %/d2,%/d0\n" \
-" move%.w %/d4,%/d2\n" \
-" move%.l %/d2,%1\n" \
-" add%.l %/d1,%/d0\n" \
-" move%.l %/d0,%0" \
+ " move%.l %2,%/d0\n" \
+ " move%.l %3,%/d1\n" \
+ " move%.l %/d0,%/d2\n" \
+ " swap %/d0\n" \
+ " move%.l %/d1,%/d3\n" \
+ " swap %/d1\n" \
+ " move%.w %/d2,%/d4\n" \
+ " mulu %/d3,%/d4\n" \
+ " mulu %/d1,%/d2\n" \
+ " mulu %/d0,%/d3\n" \
+ " mulu %/d0,%/d1\n" \
+ " move%.l %/d4,%/d0\n" \
+ " eor%.w %/d0,%/d0\n" \
+ " swap %/d0\n" \
+ " add%.l %/d0,%/d2\n" \
+ " add%.l %/d3,%/d2\n" \
+ " jcc 1f\n" \
+ " add%.l %#65536,%/d1\n" \
+ "1: swap %/d2\n" \
+ " moveq %#0,%/d0\n" \
+ " move%.w %/d2,%/d0\n" \
+ " move%.w %/d4,%/d2\n" \
+ " move%.l %/d2,%1\n" \
+ " add%.l %/d1,%/d0\n" \
+ " move%.l %/d0,%0" \
: "=g" ((USItype) (xh)), \
"=g" ((USItype) (xl)) \
: "g" ((USItype) (a)), \
#endif /* not mcf5200 */
#endif /* not mc68020 */
-/* The '020, '030, '040 and '060 have bitfield insns. */
+/* The '020, '030, '040 and '060 have bitfield insns. */
#if defined (__mc68020__) || defined(mc68020) \
|| defined(__mc68030__) || defined(mc68030) \
|| defined(__mc68040__) || defined(mc68040) \
- || defined(__mc68060__) || defined(mc68060) \
- || defined(__NeXT__)
+ || defined(__mc68060__) || defined(mc68060)
#define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
: "=d" ((USItype) (count)) \
#if defined (__m88000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addu.co %1,%r4,%r5\n" \
- "addu.ci %0,%r2,%r3" \
+ __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%rJ" ((USItype) (ah)), \
"%rJ" ((USItype) (al)), \
"rJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subu.co %1,%r4,%r5\n" \
- "subu.ci %0,%r2,%r3" \
+ __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "rJ" ((USItype) (ah)), \
"g" ((USItype) (d))); \
(r) = __xx.__i.__l; (q) = __xx.__i.__h; })
#define count_trailing_zeros(count,x) \
- do {
- __asm__ ("ffsd %2,%0" \
- : "=r" ((USItype) (count)) \
- : "0" ((USItype) 0), \
- "r" ((USItype) (x))); \
+ do { \
+ __asm__ ("ffsd %2,%0" \
+ : "=r" ((USItype) (count)) \
+ : "0" ((USItype) 0), \
+ "r" ((USItype) (x))); \
} while (0)
#endif /* __ns32000__ */
-#if (defined (_ARCH_PPC) || defined (_IBMR2))
-#if W_TYPE_SIZE == 32
+/* FIXME: We should test _IBMR2 here when we add assembly support for the
+ system vendor compilers.
+ FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
+ enough, since that hits ARM and m68k too. */
+#if (defined (_ARCH_PPC) /* AIX */ \
+ || defined (_ARCH_PWR) /* AIX */ \
+ || defined (_ARCH_COM) /* AIX */ \
+ || defined (__powerpc__) /* gcc */ \
+ || defined (__POWERPC__) /* BEOS */ \
+ || defined (__ppc__) /* Darwin */ \
+ || defined (PPC) /* GNU/Linux, SysV */ \
+ ) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%r" ((USItype) (ah)), \
- "%r" ((USItype) (al)), \
- "rI" ((USItype) (bl))); \
- else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+ else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%r" ((USItype) (ah)), \
- "%r" ((USItype) (al)), \
- "rI" ((USItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%r" ((USItype) (ah)), \
- "r" ((USItype) (bh)), \
- "%r" ((USItype) (al)), \
- "rI" ((USItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) \
+ : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (bh)), \
- "rI" ((USItype) (al)), \
- "r" ((USItype) (bl))); \
- else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
+ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+ else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (bh)), \
- "rI" ((USItype) (al)), \
- "r" ((USItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (ah)), \
- "rI" ((USItype) (al)), \
- "r" ((USItype) (bl))); \
- else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+ else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (ah)), \
- "rI" ((USItype) (al)), \
- "r" ((USItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (ah)), \
- "r" ((USItype) (bh)), \
- "rI" ((USItype) (al)), \
- "r" ((USItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) \
+ : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
#define count_leading_zeros(count, x) \
- __asm__ ("{cntlz|cntlzw} %0,%1" \
- : "=r" ((USItype) (count)) \
- : "r" ((USItype) (x)))
+ __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 32
-#if defined (_ARCH_PPC)
+#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
+ || defined (__ppc__) || defined (PPC) || defined (__vxworks__)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhwu %0,%1,%2" \
- : "=r" ((USItype) ph) \
- : "%r" (__m0), \
- "r" (__m1)); \
+ __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define UMUL_TIME 15
#define smul_ppmm(ph, pl, m0, m1) \
do { \
SItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhw %0,%1,%2" \
- : "=r" ((SItype) ph) \
- : "%r" (__m0), \
- "r" (__m1)); \
+ __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define SMUL_TIME 14
#define UDIV_TIME 120
-#else
-#define umul_ppmm(xh, xl, m0, m1) \
- do { \
- USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mul %0,%2,%3" \
- : "=r" ((USItype) (xh)), \
- "=q" ((USItype) (xl)) \
- : "r" (__m0), \
- "r" (__m1)); \
- (xh) += ((((SItype) __m0 >> 31) & __m1) \
- + (((SItype) __m1 >> 31) & __m0)); \
- } while (0)
+#elif defined (_ARCH_PWR)
#define UMUL_TIME 8
#define smul_ppmm(xh, xl, m0, m1) \
- __asm__ ("mul %0,%2,%3" \
- : "=r" ((SItype) (xh)), \
- "=q" ((SItype) (xl)) \
- : "r" (m0), \
- "r" (m1))
+ __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
#define SMUL_TIME 4
#define sdiv_qrnnd(q, r, nh, nl, d) \
- __asm__ ("div %0,%2,%4" \
- : "=r" ((SItype) (q)), "=q" ((SItype) (r)) \
- : "r" ((SItype) (nh)), "1" ((SItype) (nl)), "r" ((SItype) (d)))
+ __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
#define UDIV_TIME 100
#endif
-#else /* W_TYPE_SIZE != 32. */
-/* Must be powerpc64. */
+#endif /* 32-bit POWER architecture variants. */
+
+/* We should test _IBMR2 here when we add assembly support for the system
+ vendor compilers. */
+#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "%r" ((UDItype) (ah)), \
- "%r" ((UDItype) (al)), \
- "rI" ((UDItype) (bl))); \
- else if (__builtin_constant_p (bh) && (bh) ==~(UDItype) 0) \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+ else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "%r" ((UDItype) (ah)), \
- "%r" ((UDItype) (al)), \
- "rI" ((UDItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "%r" ((UDItype) (ah)), \
- "r" ((UDItype) (bh)), \
- "%r" ((UDItype) (al)), \
- "rI" ((UDItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) \
+ : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "r" ((UDItype) (bh)), \
- "rI" ((UDItype) (al)), \
- "r" ((UDItype) (bl))); \
- else if (__builtin_constant_p (ah) && (ah) ==~(UDItype) 0) \
+ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+ else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "r" ((UDItype) (bh)), \
- "rI" ((UDItype) (al)), \
- "r" ((UDItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "r" ((UDItype) (ah)), \
- "rI" ((UDItype) (al)), \
- "r" ((UDItype) (bl))); \
- else if (__builtin_constant_p (bh) && (bh) ==~(UDItype) 0) \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+ else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "r" ((UDItype) (ah)), \
- "rI" ((UDItype) (al)), \
- "r" ((UDItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "r" ((UDItype) (ah)), \
- "r" ((UDItype) (bh)), \
- "rI" ((UDItype) (al)), \
- "r" ((UDItype) (bl))); \
+ : "=r" (sh), "=&r" (sl) \
+ : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
-
#define count_leading_zeros(count, x) \
- __asm__ ("{cntlz|cntlzd} %0,%1" \
- : "=r" (count) \
- : "r" ((UDItype) (x)))
+ __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 64
-
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhdu %0,%1,%2" \
- : "=r" ((UDItype) ph) \
- : "%r" (__m0), \
- "r" (__m1)); \
+ __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
-#define UMUL_TIME 16
-
+#define UMUL_TIME 15
#define smul_ppmm(ph, pl, m0, m1) \
do { \
DItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhd %0,%1,%2" \
- : "=r" ((DItype) ph) \
- : "%r" (__m0), \
- "r" (__m1)); \
+ __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
-#define SMUL_TIME 16
-#define UDIV_TIME 72
-#endif /* W_TYPE_SIZE == 32 */
-#endif /* Power architecture variants. */
-
-#if defined (__pyr__) && W_TYPE_SIZE == 32
-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addw %5,%1\n" \
- "addwc %3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "%1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subw %5,%1\n" \
- "subwb %3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
-/* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
-#define umul_ppmm(w1, w0, u, v) \
- ({union {UDItype __ll; \
- struct {USItype __h, __l;} __i; \
- } __xx; \
- __asm__ ("movw %1,%R0\n" \
- "uemul %2,%0" \
- : "=&r" (__xx.__ll) \
- : "g" ((USItype) (u)), \
- "g" ((USItype) (v))); \
- (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
-#endif /* __pyr__ */
+#define SMUL_TIME 14 /* ??? */
+#define UDIV_TIME 120 /* ??? */
+#endif /* 64-bit PowerPC. */
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("a %1,%5\n" \
- "ae %0,%3" \
+ __asm__ ("a %1,%5\n\tae %0,%3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"%1" ((USItype) (al)), \
"r" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("s %1,%5\n" \
- "se %0,%3" \
+ __asm__ ("s %1,%5\n\tse %0,%3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
do { \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ( \
- "s r2,r2\n" \
- "mts r10,%2\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "m r2,%3\n" \
- "cas %0,r2,r0\n" \
- "mfs r10,%1" \
+ "s r2,r2\n" \
+" mts r10,%2\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" m r2,%3\n" \
+" cas %0,r2,r0\n" \
+" mfs r10,%1" \
: "=r" ((USItype) (ph)), \
"=r" ((USItype) (pl)) \
: "%r" (__m0), \
#if defined (__sh2__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
__asm__ ( \
- "dmulu.l %2,%3\n" \
- "sts macl,%1\n" \
- "sts mach,%0" \
+ "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
: "=r" ((USItype)(w1)), \
"=r" ((USItype)(w0)) \
: "r" ((USItype)(u)), \
#define UMUL_TIME 5
#endif
-#if defined (__sparc__) && !defined(__arch64__) \
- && !defined(__sparcv9) && W_TYPE_SIZE == 32
+#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#define count_leading_zeros(count, x) \
+ do \
+ { \
+ UDItype x_ = (USItype)(x); \
+ SItype c_; \
+ \
+ __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
+ (count) = c_ - 31; \
+ } \
+ while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+
+#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
+ && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addcc %r4,%5,%1\n" \
- "addx %r2,%3,%0" \
+ __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%rJ" ((USItype) (ah)), \
"rI" ((USItype) (bl)) \
__CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subcc %r4,%5,%1\n" \
- "subx %r2,%3,%0" \
+ __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "rJ" ((USItype) (ah)), \
"=r" ((USItype) (w0)) \
: "r" ((USItype) (u)), \
"r" ((USItype) (v)))
-#define udiv_qrnnd(q, r, n1, n0, d) \
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
__asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
- : "=&r" ((USItype) (q)), \
- "=&r" ((USItype) (r)) \
- : "r" ((USItype) (n1)), \
- "r" ((USItype) (n0)), \
- "r" ((USItype) (d)))
+ : "=&r" ((USItype) (__q)), \
+ "=&r" ((USItype) (__r)) \
+ : "r" ((USItype) (__n1)), \
+ "r" ((USItype) (__n0)), \
+ "r" ((USItype) (__d)))
#else
#if defined (__sparclite__)
/* This has hardware multiply but not divide. It also has two additional
"r" ((USItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd\n" \
-" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
-" tst %%g0\n" \
-" divscc %3,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%%g1\n" \
-" divscc %%g1,%4,%0\n" \
-" rd %%y,%1\n" \
-" bl,a 1f\n" \
-" add %1,%4,%1\n" \
+" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
+" tst %%g0\n" \
+" divscc %3,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%%g1\n" \
+" divscc %%g1,%4,%0\n" \
+" rd %%y,%1\n" \
+" bl,a 1f\n" \
+" add %1,%4,%1\n" \
"1: ! End of inline udiv_qrnnd" \
: "=r" ((USItype) (q)), \
"=r" ((USItype) (r)) \
: "g1" __AND_CLOBBER_CC)
#define UDIV_TIME 37
#define count_leading_zeros(count, x) \
- do { \
- __asm__ ("scan %1,1,%0" \
- : "=r" ((USItype) (count)) \
- : "r" ((USItype) (x))); \
+ do { \
+ __asm__ ("scan %1,1,%0" \
+ : "=r" ((USItype) (count)) \
+ : "r" ((USItype) (x))); \
} while (0)
/* Early sparclites return 63 for an argument of 0, but they warn that future
implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
(i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("! Inlined umul_ppmm\n" \
-" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
-" sra %3,31,%%o5 ! Don't move this insn\n" \
-" and %2,%%o5,%%o5 ! Don't move this insn\n" \
-" andcc %%g0,0,%%g1 ! Don't move this insn\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,%3,%%g1\n" \
-" mulscc %%g1,0,%%g1\n" \
-" add %%g1,%%o5,%0\n" \
-" rd %%y,%1" \
+" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
+" sra %3,31,%%o5 ! Don't move this insn\n" \
+" and %2,%%o5,%%o5 ! Don't move this insn\n" \
+" andcc %%g0,0,%%g1 ! Don't move this insn\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,%3,%%g1\n" \
+" mulscc %%g1,0,%%g1\n" \
+" add %%g1,%%o5,%0\n" \
+" rd %%y,%1" \
: "=r" ((USItype) (w1)), \
"=r" ((USItype) (w0)) \
: "%rI" ((USItype) (u)), \
: "g1", "o5" __AND_CLOBBER_CC)
#define UMUL_TIME 39 /* 39 instructions */
/* It's quite necessary to add this much assembler for the sparc.
- The default udiv_qrnnd (in C) is more than 10 times slower! */
-#define udiv_qrnnd(q, r, n1, n0, d) \
+ The default udiv_qrnnd (in C) is more than 10 times slower! */
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
__asm__ ("! Inlined udiv_qrnnd\n" \
" mov 32,%%g1\n" \
" subcc %1,%2,%%g0\n" \
"1: bcs 5f\n" \
-" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
+" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
" sub %1,%2,%1 ! this kills msb of n\n" \
" addx %1,%1,%1 ! so this can't give carry\n" \
" subcc %%g1,1,%%g1\n" \
"2: bne 1b\n" \
-" subcc %1,%2,%%g0\n" \
+" subcc %1,%2,%%g0\n" \
" bcs 3f\n" \
-" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
+" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
" b 3f\n" \
-" sub %1,%2,%1 ! this kills msb of n\n" \
+" sub %1,%2,%1 ! this kills msb of n\n" \
"4: sub %1,%2,%1\n" \
"5: addxcc %1,%1,%1\n" \
" bcc 2b\n" \
-" subcc %%g1,1,%%g1\n" \
+" subcc %%g1,1,%%g1\n" \
"! Got carry from n. Subtract next step to cancel this carry.\n" \
" bne 4b\n" \
-" addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
+" addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
" sub %1,%2,%1\n" \
"3: xnor %0,0,%0\n" \
-" ! End of inline udiv_qrnnd" \
- : "=&r" ((USItype) (q)), \
- "=&r" ((USItype) (r)) \
- : "r" ((USItype) (d)), \
- "1" ((USItype) (n1)), \
- "0" ((USItype) (n0)) : "g1" __AND_CLOBBER_CC)
-#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
+" ! End of inline udiv_qrnnd" \
+ : "=&r" ((USItype) (__q)), \
+ "=&r" ((USItype) (__r)) \
+ : "r" ((USItype) (__d)), \
+ "1" ((USItype) (__n1)), \
+ "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
#endif /* __sparclite__ */
#endif /* __sparc_v8__ */
-#endif /* __sparc__ */
+#endif /* sparc32 */
-#if ((defined (__sparc__) && defined (__arch64__)) \
- || defined (__sparcv9)) && W_TYPE_SIZE == 64
+#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
+ && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addcc %r4,%5,%1\n" \
- "add %r2,%3,%0\n" \
- "bcs,a,pn %%xcc, 1f\n" \
- "add %0, 1, %0\n" \
+ __asm__ ("addcc %r4,%5,%1\n\t" \
+ "add %r2,%3,%0\n\t" \
+ "bcs,a,pn %%xcc, 1f\n\t" \
+ "add %0, 1, %0\n" \
"1:" \
- : "=r" ((UDItype)(sh)), \
- "=&r" ((UDItype)(sl)) \
- : "%rJ" ((UDItype)(ah)), \
- "rI" ((UDItype)(bh)), \
- "%rJ" ((UDItype)(al)), \
- "rI" ((UDItype)(bl)) \
+ : "=r" ((UDItype)(sh)), \
+ "=&r" ((UDItype)(sl)) \
+ : "%rJ" ((UDItype)(ah)), \
+ "rI" ((UDItype)(bh)), \
+ "%rJ" ((UDItype)(al)), \
+ "rI" ((UDItype)(bl)) \
__CLOBBER_CC)
-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subcc %r4,%5,%1\n" \
- "sub %r2,%3,%0\n" \
- "bcs,a,pn %%xcc, 1f\n" \
- "sub %0, 1, %0\n" \
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+ __asm__ ("subcc %r4,%5,%1\n\t" \
+ "sub %r2,%3,%0\n\t" \
+ "bcs,a,pn %%xcc, 1f\n\t" \
+ "sub %0, 1, %0\n\t" \
"1:" \
- : "=r" ((UDItype)(sh)), \
- "=&r" ((UDItype)(sl)) \
- : "rJ" ((UDItype)(ah)), \
- "rI" ((UDItype)(bh)), \
- "rJ" ((UDItype)(al)), \
- "rI" ((UDItype)(bl)) \
+ : "=r" ((UDItype)(sh)), \
+ "=&r" ((UDItype)(sl)) \
+ : "rJ" ((UDItype)(ah)), \
+ "rI" ((UDItype)(bh)), \
+ "rJ" ((UDItype)(al)), \
+ "rI" ((UDItype)(bl)) \
__CLOBBER_CC)
#define umul_ppmm(wh, wl, u, v) \
do { \
UDItype tmp1, tmp2, tmp3, tmp4; \
__asm__ __volatile__ ( \
- "srl %7,0,%3\n" \
- "mulx %3,%6,%1\n" \
- "srlx %6,32,%2\n" \
- "mulx %2,%3,%4\n" \
- "sllx %4,32,%5\n" \
- "srl %6,0,%3\n" \
- "sub %1,%5,%5\n" \
- "srlx %5,32,%5\n" \
- "addcc %4,%5,%4\n" \
- "srlx %7,32,%5\n" \
- "mulx %3,%5,%3\n" \
- "mulx %2,%5,%5\n" \
- "sethi %%hi(0x80000000),%2\n" \
- "addcc %4,%3,%4\n" \
- "srlx %4,32,%4\n" \
- "add %2,%2,%2\n" \
- "movcc %%xcc,%%g0,%2\n" \
- "addcc %5,%4,%5\n" \
- "sllx %3,32,%3\n" \
- "add %1,%3,%1\n" \
+ "srl %7,0,%3\n\t" \
+ "mulx %3,%6,%1\n\t" \
+ "srlx %6,32,%2\n\t" \
+ "mulx %2,%3,%4\n\t" \
+ "sllx %4,32,%5\n\t" \
+ "srl %6,0,%3\n\t" \
+ "sub %1,%5,%5\n\t" \
+ "srlx %5,32,%5\n\t" \
+ "addcc %4,%5,%4\n\t" \
+ "srlx %7,32,%5\n\t" \
+ "mulx %3,%5,%3\n\t" \
+ "mulx %2,%5,%5\n\t" \
+ "sethi %%hi(0x80000000),%2\n\t" \
+ "addcc %4,%3,%4\n\t" \
+ "srlx %4,32,%4\n\t" \
+ "add %2,%2,%2\n\t" \
+ "movcc %%xcc,%%g0,%2\n\t" \
+ "addcc %5,%4,%5\n\t" \
+ "sllx %3,32,%3\n\t" \
+ "add %1,%3,%1\n\t" \
"add %5,%2,%0" \
: "=r" ((UDItype)(wh)), \
"=&r" ((UDItype)(wl)), \
#if defined (__vax__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addl2 %5,%1\n" \
- "adwc %3,%0" \
+ __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
: "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subl2 %5,%1\n" \
- "sbwc %3,%0" \
+ __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
: "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
__x1 += __ll_highpart (__x0);/* this can't give carry */ \
__x1 += __x2; /* but this indeed can */ \
if (__x1 < __x2) /* did we get it? */ \
- __x3 += __ll_B; /* yes, add it in the proper pos. */ \
+ __x3 += __ll_B; /* yes, add it in the proper pos. */ \
\
(w1) = __x3 + __ll_highpart (__x1); \
(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
#if !defined (__umulsidi3)
#define __umulsidi3(u, v) \
- ({DIunion __w; \
+ ({DWunion __w; \
umul_ppmm (__w.s.high, __w.s.low, u, v); \
__w.ll; })
#endif
projects / platform / upstream / glibc.git / commitdiff