drm/amd/display: Add missing DP_SEC register definitions and masks

[Why]
some DP_SEC register defs and masks are missing.

[How]
add the missing defs and masks.

Signed-off-by: Max Tseng <chuan-yu.tseng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9e38c37..76b3346 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -81,7 +81,9 @@
        SRI(DP_MSE_RATE_UPDATE, DP, id), \
        SRI(DP_PIXEL_FORMAT, DP, id), \
        SRI(DP_SEC_CNTL, DP, id), \
+       SRI(DP_SEC_CNTL1, DP, id), \
        SRI(DP_SEC_CNTL2, DP, id), \
+       SRI(DP_SEC_CNTL5, DP, id), \
        SRI(DP_SEC_CNTL6, DP, id), \
        SRI(DP_STEER_FIFO, DP, id), \
        SRI(DP_VID_M, DP, id), \
@@ -126,7 +128,9 @@ struct dcn10_stream_enc_registers {
        uint32_t DP_MSE_RATE_UPDATE;
        uint32_t DP_PIXEL_FORMAT;
        uint32_t DP_SEC_CNTL;
+       uint32_t DP_SEC_CNTL1;
        uint32_t DP_SEC_CNTL2;
+       uint32_t DP_SEC_CNTL5;
        uint32_t DP_SEC_CNTL6;
        uint32_t DP_STEER_FIFO;
        uint32_t DP_VID_M;
@@ -411,6 +415,8 @@ struct dcn10_stream_enc_registers {
        type DP_SEC_GSP3_ENABLE;\
        type DP_SEC_GSP4_ENABLE;\
        type DP_SEC_GSP5_ENABLE;\
+       type DP_SEC_GSP5_LINE_NUM;\
+       type DP_SEC_GSP5_LINE_REFERENCE;\
        type DP_SEC_GSP6_ENABLE;\
        type DP_SEC_GSP7_ENABLE;\
        type DP_SEC_GSP7_PPS;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
index d2a805b..9a881e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
@@ -83,6 +83,8 @@
        SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
        SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
        SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\
+       SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
+       SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
        SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh)
 
 void dcn20_stream_encoder_construct(