mmc: tegra: Configure default trim value on reset

Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike
the outbound tap value this does not depend on the signaling mode and
needs to be only programmed once.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 3fd54af..704c82c 100644 (file)
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -37,6 +37,8 @@
 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL                  0x100
 #define SDHCI_CLOCK_CTRL_TAP_MASK                      0x00ff0000
 #define SDHCI_CLOCK_CTRL_TAP_SHIFT                     16
+#define SDHCI_CLOCK_CTRL_TRIM_MASK                     0x1f000000
+#define SDHCI_CLOCK_CTRL_TRIM_SHIFT                    24
 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE         BIT(5)
 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE                BIT(3)
 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE       BIT(2)
@@ -287,7 +289,8 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
                       SDHCI_MISC_CTRL_ENABLE_DDR50 |
                       SDHCI_MISC_CTRL_ENABLE_SDR104);
 
-       clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
+       clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
+                     SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
 
        if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
                /* Erratum: Enable SDHCI spec v3.00 support */
@@ -304,6 +307,8 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
                        clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
        }
 
+       clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
+
        sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
        sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);