[NFC][AArch64] Adjust comments in tablegen file

diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 9e64b21..0a24896 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -11708,6 +11708,10 @@ multiclass MOPSMemorySetTaggingInsns<bits<2> opcode, string asm> {
   def TN : MOPSMemorySetTagging<opcode, 1, 1, asm # "tn">;
 }
 
+//----------------------------------------------------------------------------
+// 2022 Armv8.9/Armv9.4 Extensions
+//----------------------------------------------------------------------------
+
 //---
 // 2022 Architecture Extensions: General Data Processing (FEAT_CSSC)
 //---
@@ -11772,10 +11776,6 @@ multiclass ComparisonOp<bit isUnsigned, bit isMin, string asm,
                                       !not(isUnsigned) : simm8_64b), asm, OpNode>;
 }
 
-//----------------------------------------------------------------------------
-// 2022 Armv8.9/Armv9.4 Extensions
-//----------------------------------------------------------------------------
-
 //---
 // RCPC instructions (FEAT_LRCPC3)
 //---

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 3e24bcd..66b03ea 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -8571,11 +8571,15 @@ def : Pat<(AArch64AssertZExtBool GPR32:$op),
 //===----------------------------===//
 // 2022 Architecture Extensions:
 //===----------------------------===//
+
 def : InstAlias<"clrbhb",  (HINT 22), 0>;
 let Predicates = [HasCLRBHB] in {
   def : InstAlias<"clrbhb",  (HINT 22), 1>;
 }
 
+//===----------------------------------------------------------------------===//
+// Translation Hardening Extension (FEAT_THE)
+//===----------------------------------------------------------------------===//
 defm RCW     : ReadCheckWriteCompareAndSwap;
 
 defm RCWCLR  : ReadCheckWriteOperation<0b001, "clr">;