return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
}
+/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
+/// for either a value in a register or a register-indirect+offset
+/// address. The convention is that a DBG_VALUE is indirect iff the
+/// second operand is an immediate.
+///
+inline MachineInstrBuilder BuildMI(MachineFunction &MF,
+ DebugLoc DL,
+ const MCInstrDesc &MCID,
+ bool IsIndirect,
+ unsigned Reg,
+ unsigned Offset,
+ const MDNode *MD) {
+ if (IsIndirect)
+ return BuildMI(MF, DL, MCID)
+ .addReg(Reg, RegState::Debug)
+ .addImm(Offset)
+ .addMetadata(MD);
+ else {
+ assert(Offset == 0 && "A direct address cannot have an offset.");
+ return BuildMI(MF, DL, MCID)
+ .addReg(Reg, RegState::Debug)
+ .addReg(0U, RegState::Debug)
+ .addMetadata(MD);
+ }
+}
+
+/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
+/// for either a value in a register or a register-indirect+offset
+/// address and inserts it at position I.
+///
+inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
+ MachineBasicBlock::iterator I,
+ DebugLoc DL,
+ const MCInstrDesc &MCID,
+ bool IsIndirect,
+ unsigned Reg,
+ unsigned Offset,
+ const MDNode *MD) {
+ MachineFunction &MF = *BB.getParent();
+ MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD);
+ BB.insert(I, MI);
+ return MachineInstrBuilder(MF, MI);
+}
+
+
inline unsigned getDefRegState(bool B) {
return B ? RegState::Define : 0;
}
}
OS << V.getName() << " <- ";
- int64_t Offset = MI->getOperand(1).getImm();
- bool Deref = false;
+ // The second operand is only an offset if it's an immediate.
+ bool Deref = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();
+ int64_t Offset = Deref ? MI->getOperand(1).getImm() : 0;
+
// Register or immediate value. Register 0 means undef.
if (MI->getOperand(0).isFPImm()) {
APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF());
unsigned Reg;
if (MI->getOperand(0).isReg()) {
Reg = MI->getOperand(0).getReg();
- Deref = Offset != 0; // FIXME: use a better sentinel value so that deref
- // of a reg with a zero offset is valid
} else {
assert(MI->getOperand(0).isFI() && "Unknown operand type");
const TargetFrameLowering *TFI = AP.TM.getFrameLowering();
OS << AP.TM.getRegisterInfo()->getName(Reg);
}
- if (Offset)
- OS << '+' << Offset;
if (Deref)
- OS << ']';
+ OS << '+' << Offset << ']';
+
// NOTE: Want this comment at start of line, don't emit with AddComment.
AP.OutStreamer.EmitRawText(OS.str());
return true;
assert(DVInsn->getNumOperands() == 3);
if (DVInsn->getOperand(0).isReg()) {
const MachineOperand RegOp = DVInsn->getOperand(0);
- if (int64_t Offset = DVInsn->getOperand(1).getImm()) {
- MachineLocation Location(RegOp.getReg(), Offset);
+ // If the second operand is an immedieate, this is an indirect value.
+ if (DVInsn->getOperand(1).isImm()) {
+ MachineLocation Location(RegOp.getReg(), DVInsn->getOperand(1).getImm());
addVariableAddress(*DV, VariableDie, Location);
} else if (RegOp.getReg())
addVariableAddress(*DV, VariableDie, MachineLocation(RegOp.getReg()));
assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
return MI->getNumOperands() == 3 &&
MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&
- MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;
+ (MI->getOperand(1).isImm() ||
+ (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == 0U));
}
// Get .debug_loc entry for the instruction range starting at MI.
const MDNode *Var = MI->getOperand(MI->getNumOperands() - 1).getMetadata();
assert(MI->getNumOperands() == 3);
- if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {
+ if (MI->getOperand(0).isReg()) {
MachineLocation MLoc;
- // TODO: Currently an offset of 0 in a DBG_VALUE means
- // we need to generate a direct register value.
- // There is no way to specify an indirect value with offset 0.
- if (MI->getOperand(1).getImm() == 0)
+ // If the second operand is an immediate, this is a
+ // register-indirect address.
+ if (!MI->getOperand(1).isImm())
MLoc.set(MI->getOperand(0).getReg());
else
MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
class UserValue {
const MDNode *variable; ///< The debug info variable we are part of.
unsigned offset; ///< Byte offset into variable.
+ bool IsIndirect; ///< true if this is a register-indirect+offset value.
DebugLoc dl; ///< The debug location for the variable. This is
///< used by dwarf writer to find lexical scope.
UserValue *leader; ///< Equivalence class leader.
public:
/// UserValue - Create a new UserValue.
- UserValue(const MDNode *var, unsigned o, DebugLoc L,
+ UserValue(const MDNode *var, unsigned o, bool i, DebugLoc L,
LocMap::Allocator &alloc)
- : variable(var), offset(o), dl(L), leader(this), next(0), locInts(alloc)
+ : variable(var), offset(o), IsIndirect(i), dl(L), leader(this),
+ next(0), locInts(alloc)
{}
/// getLeader - Get the leader of this value's equivalence class.
UVMap userVarMap;
/// getUserValue - Find or create a UserValue.
- UserValue *getUserValue(const MDNode *Var, unsigned Offset, DebugLoc DL);
+ UserValue *getUserValue(const MDNode *Var, unsigned Offset,
+ bool IsIndirect, DebugLoc DL);
/// lookupVirtReg - Find the EC leader for VirtReg or null.
UserValue *lookupVirtReg(unsigned VirtReg);
}
UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset,
- DebugLoc DL) {
+ bool IsIndirect, DebugLoc DL) {
UserValue *&Leader = userVarMap[Var];
if (Leader) {
UserValue *UV = Leader->getLeader();
return UV;
}
- UserValue *UV = new UserValue(Var, Offset, DL, allocator);
+ UserValue *UV = new UserValue(Var, Offset, IsIndirect, DL, allocator);
userValues.push_back(UV);
Leader = UserValue::merge(Leader, UV);
return UV;
bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
// DBG_VALUE loc, offset, variable
if (MI->getNumOperands() != 3 ||
- !MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
+ !(MI->getOperand(1).isReg() || MI->getOperand(1).isImm()) ||
+ !MI->getOperand(2).isMetadata()) {
DEBUG(dbgs() << "Can't handle " << *MI);
return false;
}
// Get or create the UserValue for (variable,offset).
- unsigned Offset = MI->getOperand(1).getImm();
+ bool IsIndirect = MI->getOperand(1).isImm();
+ unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
const MDNode *Var = MI->getOperand(2).getMetadata();
- UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc());
+ UserValue *UV = getUserValue(Var, Offset, IsIndirect, MI->getDebugLoc());
UV->addDef(Idx, MI->getOperand(0));
return true;
}
MachineOperand &Loc = locations[LocNo];
++NumInsertedDebugValues;
- BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
- .addOperand(Loc).addImm(offset).addMetadata(variable);
+ if (Loc.isReg())
+ BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
+ IsIndirect, Loc.getReg(), offset, variable);
+ else
+ BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
+ .addOperand(Loc).addImm(offset).addMetadata(variable);
}
void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
MachineInstr *DBG = LRIDbgValues[li];
const MDNode *MDPtr = DBG->getOperand(2).getMetadata();
- int64_t Offset = DBG->getOperand(1).getImm();
+ bool IsIndirect = DBG->getOperand(1).isImm(); // Register-indirect value?
+ int64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0;
DebugLoc DL;
if (MI == MBB->end()) {
// If MI is at basic block end then use last instruction's location.
return true;
}
+ unsigned Offset = 0;
Optional<MachineOperand> Op;
if (const Argument *Arg = dyn_cast<Argument>(Address))
// Some arguments' frame index is recorded during argument lowering.
- if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
- Op = MachineOperand::CreateFI(FI);
+ Offset = FuncInfo.getArgumentFrameIndex(Arg);
+ if (Offset)
+ Op = MachineOperand::CreateFI(Offset);
if (!Op)
if (unsigned Reg = lookUpRegForValue(Address))
Op = MachineOperand::CreateReg(Reg, false);
Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
false);
- if (Op && Op->isReg())
- Op->setIsDebug(true);
-
if (Op)
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)
+ if (Op->isReg()) {
+ Op->setIsDebug(true);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(TargetOpcode::DBG_VALUE),
+ /* IsIndirect */ DI->getAddress()->getType()->isPointerTy(),
+ Op->getReg(), Offset, DI->getVariable());
+ } else
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)
.addMetadata(DI->getVariable());
else
// We can't yet handle anything else here because it would require
.addFPImm(CF).addImm(DI->getOffset())
.addMetadata(DI->getVariable());
} else if (unsigned Reg = lookUpRegForValue(V)) {
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
- .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
- .addMetadata(DI->getVariable());
+ bool IsIndirect = DI->getOffset() != 0;
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, IsIndirect,
+ Reg, DI->getOffset(), DI->getVariable());
} else {
// We can't yet handle anything else here because it would require
// generating code, thus altering codegen because of debug info.
MIB.addReg(0U);
}
- MIB.addImm(Offset).addMetadata(MDPtr);
+ if (Offset != 0) // Indirect addressing.
+ MIB.addImm(Offset);
+ else
+ MIB.addReg(0U, RegState::Debug);
+
+ MIB.addMetadata(MDPtr);
+
return &*MIB;
}
return false;
if (Op->isReg())
- Op->setIsDebug();
-
- FuncInfo.ArgDbgValues.push_back(
+ FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
+ TII->get(TargetOpcode::DBG_VALUE),
+ /* IsIndirect */ Offset != 0,
+ Op->getReg(), Offset, Variable));
+ else
+ FuncInfo.ArgDbgValues.push_back(
BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
.addOperand(*Op).addImm(Offset).addMetadata(Variable));
+
return true;
}
MachineBasicBlock::iterator InsertPos = Def;
const MDNode *Variable =
MI->getOperand(MI->getNumOperands()-1).getMetadata();
- unsigned Offset = MI->getOperand(1).getImm();
+ bool IsIndirect = MI->getOperand(1).isImm();
+ unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
// Def is never a terminator here, so it is ok to increment InsertPos.
BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
- TII.get(TargetOpcode::DBG_VALUE))
- .addReg(LDI->second, RegState::Debug)
- .addImm(Offset).addMetadata(Variable);
+ TII.get(TargetOpcode::DBG_VALUE),
+ IsIndirect,
+ LDI->second, Offset, Variable);
// If this vreg is directly copied into an exported register then
// that COPY instructions also need DBG_VALUE, if it is the only
if (CopyUseMI) {
MachineInstr *NewMI =
BuildMI(*MF, CopyUseMI->getDebugLoc(),
- TII.get(TargetOpcode::DBG_VALUE))
- .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
- .addImm(Offset).addMetadata(Variable);
+ TII.get(TargetOpcode::DBG_VALUE),
+ IsIndirect,
+ CopyUseMI->getOperand(0).getReg(),
+ Offset, Variable);
MachineBasicBlock::iterator Pos = CopyUseMI;
EntryMBB->insertAfter(Pos, NewMI);
}
!21 = metadata !{metadata !6, metadata !11}
!22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"}
-; Check that variable bar:b value range is appropriately trucated in debug info.
+; Check that variable bar:b value range is appropriately truncated in debug info.
; The variable is in %rdi which is clobbered by 'movl %ebx, %edi'
; Here Ltmp7 is the end of the location range.
;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}
;CHECK-NEXT: .short Lset
;CHECK-NEXT: Ltmp
-;CHECK-NEXT: .byte 85
+;CHECK-NEXT: .byte 85 ## DW_OP_reg
;CHECK-NEXT: Ltmp
;CHECK-NEXT: .quad 0
;CHECK-NEXT: .quad 0
; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o %t -filetype=obj
-; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s -check-prefix=DW-CHECK
-; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
+; DW-CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
; FIXME: The location here needs to be fixed, but llvm-dwarfdump doesn't handle
; DW_AT_location lists yet.
-; CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)
+; DW-CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)
+
+; Unfortunately llvm-dwarfdump can't unparse a list of DW_AT_locations
+; right now, so we check the asm output:
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK
+; vla should have a register-indirect address at one point.
+; ASM-CHECK: DEBUG_VALUE: vla <- [RCX+0]
define void @testVLAwithSize(i32 %s) nounwind uwtable ssp {
entry:
; CHECK: debug_info contents
; CHECK: DW_AT_name{{.*}} = "f"
-; 0x74 is DW_OP_breg0 + 4, showing that the parameter is accessed indirectly
+; 0x74 is DW_OP_breg4, showing that the parameter is accessed indirectly
; (with a zero offset) from the register parameter
-; CHECK: DW_AT_location{{.*}}(<0x02> 74 00 )
+; CHECK: DW_AT_location{{.*}}(<0x0{{.}}> 74 00
; CHECK: DW_AT_name{{.*}} = "g"
; CHECK: DW_AT_location{{.*}}([[G_LOC:0x[0-9]*]])
--- /dev/null
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s
+; Ensure that we generate a breg+0 location for the variable length array a.
+; CHECK: ##DEBUG_VALUE: vla:a <- [RDX+0]
+; rdar://problem/13658587
+;
+; generated from:
+;
+; int vla(int n) {
+; int a[n];
+; a[0] = 42;
+; return a[n-1];
+; }
+;
+; int main(int argc, char** argv) {
+; return vla(argc);
+; }
+
+; ModuleID = 'vla.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @vla(i32 %n) nounwind ssp uwtable {
+entry:
+ %n.addr = alloca i32, align 4
+ %saved_stack = alloca i8*
+ %cleanup.dest.slot = alloca i32
+ store i32 %n, i32* %n.addr, align 4
+ call void @llvm.dbg.declare(metadata !{i32* %n.addr}, metadata !15), !dbg !16
+ %0 = load i32* %n.addr, align 4, !dbg !17
+ %1 = zext i32 %0 to i64, !dbg !17
+ %2 = call i8* @llvm.stacksave(), !dbg !17
+ store i8* %2, i8** %saved_stack, !dbg !17
+ %vla = alloca i32, i64 %1, align 16, !dbg !17
+ call void @llvm.dbg.declare(metadata !{i32* %vla}, metadata !18), !dbg !17
+ %arrayidx = getelementptr inbounds i32* %vla, i64 0, !dbg !22
+ store i32 42, i32* %arrayidx, align 4, !dbg !22
+ %3 = load i32* %n.addr, align 4, !dbg !23
+ %sub = sub nsw i32 %3, 1, !dbg !23
+ %idxprom = sext i32 %sub to i64, !dbg !23
+ %arrayidx1 = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23
+ %4 = load i32* %arrayidx1, align 4, !dbg !23
+ store i32 1, i32* %cleanup.dest.slot
+ %5 = load i8** %saved_stack, !dbg !24
+ call void @llvm.stackrestore(i8* %5), !dbg !24
+ ret i32 %4, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+; Function Attrs: nounwind
+declare i8* @llvm.stacksave() nounwind
+
+; Function Attrs: nounwind
+declare void @llvm.stackrestore(i8*) nounwind
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @main(i32 %argc, i8** %argv) nounwind ssp uwtable {
+entry:
+ %retval = alloca i32, align 4
+ %argc.addr = alloca i32, align 4
+ %argv.addr = alloca i8**, align 8
+ store i32 0, i32* %retval
+ store i32 %argc, i32* %argc.addr, align 4
+ call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !25), !dbg !26
+ store i8** %argv, i8*** %argv.addr, align 8
+ call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !27), !dbg !26
+ %0 = load i32* %argc.addr, align 4, !dbg !28
+ %call = call i32 @vla(i32 %0), !dbg !28
+ ret i32 %call, !dbg !28
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/vla.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"vla.c", metadata !""}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4, metadata !9}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"vla", metadata !"vla", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @vla, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [vla]
+!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/vla.c]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8, metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !2, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
+!10 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = metadata !{metadata !8, metadata !8, metadata !12}
+!12 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
+!13 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
+!14 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!15 = metadata !{i32 786689, metadata !4, metadata !"n", metadata !5, i32 16777217, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [n] [line 1]
+!16 = metadata !{i32 1, i32 0, metadata !4, null}
+!17 = metadata !{i32 2, i32 0, metadata !4, null}
+!18 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32 2, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 2]
+!19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !8, metadata !20, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
+!20 = metadata !{metadata !21}
+!21 = metadata !{i32 786465, i64 0, i64 -1} ; [ DW_TAG_subrange_type ] [unbounded]
+!22 = metadata !{i32 3, i32 0, metadata !4, null}
+!23 = metadata !{i32 4, i32 0, metadata !4, null}
+!24 = metadata !{i32 5, i32 0, metadata !4, null}
+!25 = metadata !{i32 786689, metadata !9, metadata !"argc", metadata !5, i32 16777223, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc] [line 7]
+!26 = metadata !{i32 7, i32 0, metadata !9, null}
+!27 = metadata !{i32 786689, metadata !9, metadata !"argv", metadata !5, i32 33554439, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv] [line 7]
+!28 = metadata !{i32 8, i32 0, metadata !9, null}
projects / platform / upstream / llvm.git / commitdiff