When doing a (narrowing) right shift by half the width of the original type then
we are essentially shuffling the top bits from the first number down.
If we have a hi/lo pair we can just use a single shuffle instead of needing two
shifts.
i.e.
typedef short int16_t;
typedef unsigned short uint16_t;
void foo (uint16_t * restrict a, int16_t * restrict d, int n)
{
for( int i = 0; i < n; i++ )
d[i] = (a[i] * a[i]) >> 16;
}
now generates:
.L4:
ldr q0, [x0, x3]
umull v1.4s, v0.4h, v0.4h
umull2 v0.4s, v0.8h, v0.8h
uzp2 v0.8h, v1.8h, v0.8h
str q0, [x1, x3]
add x3, x3, 16
cmp x4, x3
bne .L4
instead of
.L4:
ldr q0, [x0, x3]
umull v1.4s, v0.4h, v0.4h
umull2 v0.4s, v0.8h, v0.8h
sshr v1.4s, v1.4s, 16
sshr v0.4s, v0.4s, 16
xtn v1.4h, v1.4s
xtn2 v1.8h, v0.4s
str q1, [x1, x3]
add x3, x3, 16
cmp x4, x3
bne .L4
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(*aarch64_<srn_op>topbits_shuffle<mode>_le): New.
(*aarch64_topbits_shuffle<mode>_le): New.
(*aarch64_<srn_op>topbits_shuffle<mode>_be): New.
(*aarch64_topbits_shuffle<mode>_be): New.
* config/aarch64/predicates.md
(aarch64_simd_shift_imm_vec_exact_top): New.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/shrn-combine-10.c: New test.
* gcc.target/aarch64/shrn-combine-5.c: New test.
* gcc.target/aarch64/shrn-combine-6.c: New test.
* gcc.target/aarch64/shrn-combine-7.c: New test.
* gcc.target/aarch64/shrn-combine-8.c: New test.
* gcc.target/aarch64/shrn-combine-9.c: New test.
[(set_attr "type" "neon_shift_imm_narrow_q")]
)
+(define_insn "*aarch64_<srn_op>topbits_shuffle<mode>_le"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (truncate:<VNARROWQ>
+ (SHIFTRT:VQN (match_operand:VQN 1 "register_operand" "w")
+ (match_operand:VQN 2 "aarch64_simd_shift_imm_vec_exact_top")))
+ (truncate:<VNARROWQ>
+ (SHIFTRT:VQN (match_operand:VQN 3 "register_operand" "w")
+ (match_dup 2)))))]
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+ "uzp2\\t%0.<V2ntype>, %1.<V2ntype>, %3.<V2ntype>"
+ [(set_attr "type" "neon_permute<q>")]
+)
+
+(define_insn "*aarch64_topbits_shuffle<mode>_le"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (unspec:<VNARROWQ> [
+ (match_operand:VQN 1 "register_operand" "w")
+ (match_operand:VQN 2 "aarch64_simd_shift_imm_vec_exact_top")
+ ] UNSPEC_RSHRN)
+ (unspec:<VNARROWQ> [
+ (match_operand:VQN 3 "register_operand" "w")
+ (match_dup 2)
+ ] UNSPEC_RSHRN)))]
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+ "uzp2\\t%0.<V2ntype>, %1.<V2ntype>, %3.<V2ntype>"
+ [(set_attr "type" "neon_permute<q>")]
+)
+
+(define_insn "*aarch64_<srn_op>topbits_shuffle<mode>_be"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (truncate:<VNARROWQ>
+ (SHIFTRT:VQN (match_operand:VQN 3 "register_operand" "w")
+ (match_operand:VQN 2 "aarch64_simd_shift_imm_vec_exact_top")))
+ (truncate:<VNARROWQ>
+ (SHIFTRT:VQN (match_operand:VQN 1 "register_operand" "w")
+ (match_dup 2)))))]
+ "TARGET_SIMD && BYTES_BIG_ENDIAN"
+ "uzp2\\t%0.<V2ntype>, %1.<V2ntype>, %3.<V2ntype>"
+ [(set_attr "type" "neon_permute<q>")]
+)
+
+(define_insn "*aarch64_topbits_shuffle<mode>_be"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (unspec:<VNARROWQ> [
+ (match_operand:VQN 3 "register_operand" "w")
+ (match_operand:VQN 2 "aarch64_simd_shift_imm_vec_exact_top")
+ ] UNSPEC_RSHRN)
+ (unspec:<VNARROWQ> [
+ (match_operand:VQN 1 "register_operand" "w")
+ (match_dup 2)
+ ] UNSPEC_RSHRN)))]
+ "TARGET_SIMD && BYTES_BIG_ENDIAN"
+ "uzp2\\t%0.<V2ntype>, %1.<V2ntype>, %3.<V2ntype>"
+ [(set_attr "type" "neon_permute<q>")]
+)
+
(define_expand "aarch64_shrn<mode>"
[(set (match_operand:<VNARROWQ> 0 "register_operand")
(truncate:<VNARROWQ>
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 1, 64)")))
+(define_predicate "aarch64_simd_shift_imm_vec_exact_top"
+ (and (match_code "const_vector")
+ (match_test "aarch64_const_vec_all_same_in_range_p (op,
+ GET_MODE_UNIT_BITSIZE (GET_MODE (op)) / 2,
+ GET_MODE_UNIT_BITSIZE (GET_MODE (op)) / 2)")))
+
(define_predicate "aarch64_simd_shift_imm_vec_qi"
(and (match_code "const_vector")
(match_test "aarch64_const_vec_all_same_in_range_p (op, 1, 8)")))
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+
+#include <arm_neon.h>
+
+uint32x4_t foo (uint64x2_t a, uint64x2_t b)
+{
+ return vrshrn_high_n_u64 (vrshrn_n_u64 (a, 32), b, 32);
+}
+
+/* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tshrn\t} } } */
+/* { dg-final { scan-assembler-not {\tshrn2\t} } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define TYPE1 char
+#define TYPE2 short
+#define SHIFT 8
+
+void foo (TYPE2 * restrict a, TYPE1 * restrict d, int n)
+{
+ for( int i = 0; i < n; i++ )
+ d[i] = a[i] >> SHIFT;
+}
+
+/* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tshrn\t} } } */
+/* { dg-final { scan-assembler-not {\tshrn2\t} } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define TYPE1 short
+#define TYPE2 int
+#define SHIFT 16
+
+void foo (TYPE2 * restrict a, TYPE1 * restrict d, int n)
+{
+ for( int i = 0; i < n; i++ )
+ d[i] = a[i] >> SHIFT;
+}
+
+/* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tshrn\t} } } */
+/* { dg-final { scan-assembler-not {\tshrn2\t} } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define TYPE1 int
+#define TYPE2 long long
+#define SHIFT 32
+
+void foo (TYPE2 * restrict a, TYPE1 * restrict d, int n)
+{
+ for( int i = 0; i < n; i++ )
+ d[i] = a[i] >> SHIFT;
+}
+
+/* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tshrn\t} } } */
+/* { dg-final { scan-assembler-not {\tshrn2\t} } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+
+#include <arm_neon.h>
+
+uint8x16_t foo (uint16x8_t a, uint16x8_t b)
+{
+ return vrshrn_high_n_u16 (vrshrn_n_u16 (a, 8), b, 8);
+}
+
+/* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tshrn\t} } } */
+/* { dg-final { scan-assembler-not {\tshrn2\t} } } */
--- /dev/null
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+
+#include <arm_neon.h>
+
+uint16x8_t foo (uint32x4_t a, uint32x4_t b)
+{
+ return vrshrn_high_n_u32 (vrshrn_n_u32 (a, 16), b, 16);
+}
+
+/* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tshrn\t} } } */
+/* { dg-final { scan-assembler-not {\tshrn2\t} } } */