iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500

There is only one platform, which needs special care in the reset
function, the SDM845. Add special handler for sdm845 and drop the
qcom_smmu500_reset() function.

Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221114170635.1406534-8-dmitry.baryshkov@linaro.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index e611941..6dc7fa9 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
 {
        int ret;
 
+       arm_mmu500_reset(smmu);
+
        /*
         * To address performance degradation in non-real time clients,
         * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
@@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
        return ret;
 }
 
-static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
-{
-       const struct device_node *np = smmu->dev->of_node;
-
-       arm_mmu500_reset(smmu);
-
-       if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
-               return qcom_sdm845_smmu500_reset(smmu);
-
-       return 0;
-}
-
 static const struct arm_smmu_impl qcom_smmu_impl = {
        .init_context = qcom_smmu_init_context,
        .cfg_probe = qcom_smmu_cfg_probe,
        .def_domain_type = qcom_smmu_def_domain_type,
-       .reset = qcom_smmu500_reset,
+       .reset = arm_mmu500_reset,
+       .write_s2cr = qcom_smmu_write_s2cr,
+       .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl sdm845_smmu_500_impl = {
+       .init_context = qcom_smmu_init_context,
+       .cfg_probe = qcom_smmu_cfg_probe,
+       .def_domain_type = qcom_smmu_def_domain_type,
+       .reset = qcom_sdm845_smmu500_reset,
        .write_s2cr = qcom_smmu_write_s2cr,
        .tlb_sync = qcom_smmu_tlb_sync,
 };
@@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
 static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
        .init_context = qcom_adreno_smmu_init_context,
        .def_domain_type = qcom_smmu_def_domain_type,
-       .reset = qcom_smmu500_reset,
+       .reset = arm_mmu500_reset,
        .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
        .write_sctlr = qcom_adreno_smmu_write_sctlr,
        .tlb_sync = qcom_smmu_tlb_sync,
@@ -450,6 +449,14 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
        .adreno_impl = &qcom_adreno_smmu_impl,
 };
 
+static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
+       .impl = &sdm845_smmu_500_impl,
+       /*
+        * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
+        * by the separate sdm845-smmu-v2 device.
+        */
+};
+
 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
        { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
        { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
@@ -461,7 +468,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
        { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
        { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
        { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
-       { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
+       { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
        { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_data },
        { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
        { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },