import("//llvm/utils/TableGen/tablegen.gni")
tablegen("AArch64GenAsmMatcher") {
- visibility = [ ":AsmParser" ]
+ visibility = [
+ ":AsmParser",
+ "//llvm/lib/Target/AArch64:LLVMAArch64CodeGen",
+ ]
args = [ "-gen-asm-matcher" ]
td_file = "../AArch64.td"
}
import("//llvm/utils/TableGen/tablegen.gni")
-tablegen("AArch64GenAsmMatcher") {
- visibility = [ ":LLVMAArch64CodeGen" ]
- args = [ "-gen-asm-matcher" ]
- td_file = "AArch64.td"
-}
-
tablegen("AArch64GenCallingConv") {
visibility = [ ":LLVMAArch64CodeGen" ]
args = [ "-gen-callingconv" ]
static_library("LLVMAArch64CodeGen") {
deps = [
- ":AArch64GenAsmMatcher",
":AArch64GenCallingConv",
":AArch64GenDAGISel",
":AArch64GenFastISel",
":AArch64GenGlobalISel",
":AArch64GenMCPseudoLowering",
":AArch64GenRegisterBank",
- "AsmParser",
+
+ # See https://reviews.llvm.org/D69130
+ "AsmParser:AArch64GenAsmMatcher",
"MCTargetDesc",
"TargetInfo",
"Utils",
import("//llvm/utils/TableGen/tablegen.gni")
tablegen("RISCVGenAsmMatcher") {
- visibility = [ ":AsmParser" ]
+ visibility = [
+ ":AsmParser",
+ "//llvm/lib/Target/RISCV:LLVMRISCVCodeGen",
+ ]
args = [ "-gen-asm-matcher" ]
td_file = "../RISCV.td"
}