crypto:starfive: Write the security clock tree and reset description file

Write the security clock tree and reset description file

Signed-off-by: william.qiu <william.qiu@starfivetech.com>

diff --git a/Documentation/devicetree/bindings/crypto/starfive-sec.yaml b/Documentation/devicetree/bindings/crypto/starfive-sec.yaml
new file mode 100644 (file)
index 0000000..d074c0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/starfive-sec.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/starfive-sec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SEC controller Device Tree Bindings
+
+properties:
+    compatible:
+        const:starfive,jh7110-sec
+
+    reg:
+        minItem: 1
+
+    reg-names:
+        minItem: 1
+        items:
+            -const:secreg
+            -const:secdma
+
+    interrupts:
+        minItem: 1
+
+    interrupt-names:
+        minItem: 1
+        items:
+            -const:secirq
+            -const:secdma
+
+    clocks:
+        minItem: 1
+        items:
+            -description:sec_hclk clock
+            -description:sec_ahb clock
+
+    clock-names:
+        minItem: 1
+        items:
+            -const:sec_hclk
+            -const:sec_ahb
+
+    resets:
+        minItem: 1
+        items:
+            -description:sec_hre reset
+
+    reset-names:
+        minItem: 1
+        items:
+            -const:sec_hre
+
+required:
+    - compatible
+    - reg
+    - reg-names
+    - interrupts
+    - interrupt-names
+    - clocks
+    - clock-names
+    - resets
+    - reset-names
+
+additionalProperties:false
+
+examples:
+    - |
+        crypto: crypto@16000000 {
+        compatible = "starfive,jh7110-sec";
+        reg = <0x0 0x16000000 0x0 0x4000>,
+              <0x0 0x16008000 0x0 0x4000>;
+        reg-names = "secreg","secdma";
+        interrupts = <28>, <29>;
+        interrupt-names = "secirq",
+                "dmairq";
+        clocks = <&clkgen JH7110_SEC_HCLK>,
+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
+        clock-names = "sec_hclk","sec_ahb";
+        resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+        reset-names = "sec_hre";
+        };