arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks

The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7671f15..f6514c0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3995,8 +3995,11 @@
 
                system-cache-controller@19200000 {
                        compatible = "qcom,sm8450-llcc";
-                       reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
-                       reg-names = "llcc_base", "llcc_broadcast_base";
+                       reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
+                             <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
+                             <0 0x19a00000 0 0x80000>;
+                       reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+                                   "llcc3_base", "llcc_broadcast_base";
                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
                };