ARM64: Enable Varargs with float argument.

Fixes https://github.com/dotnet/coreclr/issues/2989
ARM64 ABI does not allow float register arguments for vararg calls.
All such float arguments should be copied to integer registers.
In Lower, I explicitly add a GT_COPY for such case and support the code-gen
to expand it properly using `fmov`.
I also skip genFnPrologCalleeRegArgs() for vararg since we've already
saved all integer registers in the prolog.

Commit migrated from https://github.com/dotnet/coreclr/commit/3b6637462b86bb921857b71973400cedcd97614b

diff --git a/src/coreclr/src/jit/codegenarm64.cpp b/src/coreclr/src/jit/codegenarm64.cpp
index bbc46db..031131b 100644 (file)
--- a/src/coreclr/src/jit/codegenarm64.cpp
+++ b/src/coreclr/src/jit/codegenarm64.cpp
@@ -4753,26 +4753,7 @@ void CodeGen::genRegCopy(GenTree* treeNode)
 
     if (varTypeIsFloating(treeNode) != varTypeIsFloating(op1))
     {
-#if 0
-        instruction ins;
-        regNumber fpReg;
-        regNumber intReg;
-        if(varTypeIsFloating(treeNode))
-        {
-            ins = INS_mov_i2xmm;
-            fpReg = targetReg;
-            intReg = op1->gtRegNum;
-        }
-        else
-        {
-            ins = INS_mov_xmm2i;
-            intReg = targetReg;
-            fpReg = op1->gtRegNum;
-        }
-        inst_RV_RV(ins, fpReg, intReg, targetType);
-#else
-        NYI_ARM64("CodeGen - FP/Int RegCopy");
-#endif
+        inst_RV_RV(INS_fmov, targetReg, genConsumeReg(op1), targetType);
     }
     else
     {

diff --git a/src/coreclr/src/jit/codegencommon.cpp b/src/coreclr/src/jit/codegencommon.cpp
index d4e7169..0a1098b 100644 (file)
--- a/src/coreclr/src/jit/codegencommon.cpp
+++ b/src/coreclr/src/jit/codegencommon.cpp
@@ -3882,6 +3882,14 @@ void            CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg,
     if (verbose) 
         printf("*************** In genFnPrologCalleeRegArgs() for %s regs\n", regState->rsIsFloat ? "float" : "int");
 #endif
+#ifdef _TARGET_ARM64_
+    if (compiler->info.compIsVarArgs)
+    {
+        // We've already saved all int registers at the top of stack in the prolog.
+        // No need further action.
+        return;
+    }
+#endif
 
     assert(compiler->compGeneratingProlog);
     noway_assert(regState->rsCalleeRegArgMaskLiveIn != 0);

diff --git a/src/coreclr/src/jit/lower.cpp b/src/coreclr/src/jit/lower.cpp
index 7d0e211..c09eff4 100644 (file)
--- a/src/coreclr/src/jit/lower.cpp
+++ b/src/coreclr/src/jit/lower.cpp
@@ -1499,6 +1499,25 @@ void Lowering::LowerArg(GenTreeCall* call, GenTreePtr* ppArg)
         else
 #endif // !defined(_TARGET_64BIT_)
         {
+
+#ifdef _TARGET_ARM64_
+            // For vararg call, reg args should be all integer.
+            // Insert a copy to move float value to integer register.
+            if (call->IsVarargs() && varTypeIsFloating(type))
+            {
+                var_types intType = (type == TYP_DOUBLE) ? TYP_LONG : TYP_INT;
+                GenTreePtr intArg = comp->gtNewOperNode(GT_COPY, intType, arg);
+
+                intArg->CopyCosts(arg);
+                info->node = intArg;
+                SpliceInUnary(call, ppArg, intArg);
+
+                // Update arg/type with new ones.
+                arg = intArg;
+                type = intType;
+            }
+#endif
+
             putArg = NewPutArg(call, arg, info, type);
 
             // In the case of register passable struct (in one or two registers)

diff --git a/src/coreclr/tests/arm64/Tests.lst b/src/coreclr/tests/arm64/Tests.lst
index 17d714e..64240dd 100644 (file)
--- a/src/coreclr/tests/arm64/Tests.lst
+++ b/src/coreclr/tests/arm64/Tests.lst
@@ -11974,21 +11974,21 @@ RelativePath=JIT\jit64\mcc\interop\mcc_i80\mcc_i80.cmd
 WorkingDir=JIT\jit64\mcc\interop\mcc_i80
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;EXPECTED_FAIL;ISSUE_2989
+Categories=Pri0;EXPECTED_PASS
 HostStyle=0
 [mcc_i81.cmd_1741]
 RelativePath=JIT\jit64\mcc\interop\mcc_i81\mcc_i81.cmd
 WorkingDir=JIT\jit64\mcc\interop\mcc_i81
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;EXPECTED_FAIL
+Categories=Pri0;EXPECTED_PASS
 HostStyle=0
 [mcc_i82.cmd_1742]
 RelativePath=JIT\jit64\mcc\interop\mcc_i82\mcc_i82.cmd
 WorkingDir=JIT\jit64\mcc\interop\mcc_i82
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;EXPECTED_FAIL;ISSUE_2989
+Categories=Pri0;EXPECTED_PASS
 HostStyle=0
 [mcc_i83.cmd_1743]
 RelativePath=JIT\jit64\mcc\interop\mcc_i83\mcc_i83.cmd
@@ -32099,7 +32099,7 @@ RelativePath=JIT\Regression\CLR-x86-JIT\V1-M09.5-PDC\b16423\b16423\b16423.cmd
 WorkingDir=JIT\Regression\CLR-x86-JIT\V1-M09.5-PDC\b16423\b16423
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;JIT;EXPECTED_FAIL;ISSUE_2925;ISSUE_2989
+Categories=Pri0;JIT;EXPECTED_PASS
 HostStyle=0
 [b16498.cmd_4680]
 RelativePath=JIT\Regression\CLR-x86-JIT\V1-M09.5-PDC\b16498\b16498\b16498.cmd
@@ -32841,7 +32841,7 @@ RelativePath=JIT\Regression\CLR-x86-JIT\V1-M09.5-PDC\b32374\b32374\b32374.cmd
 WorkingDir=JIT\Regression\CLR-x86-JIT\V1-M09.5-PDC\b32374\b32374
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;JIT;EXPECTED_FAIL;ISSUE_2989
+Categories=Pri0;JIT;EXPECTED_PASS
 HostStyle=0
 [b32551a.cmd_4786]
 RelativePath=JIT\Regression\CLR-x86-JIT\V1-M09.5-PDC\b32551\b32551a\b32551a.cmd
@@ -33681,7 +33681,7 @@ RelativePath=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b41391\b41391\b41391.cmd
 WorkingDir=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b41391\b41391
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;JIT;EXPECTED_FAIL;ISSUE_2989
+Categories=Pri0;JIT;EXPECTED_PASS
 HostStyle=0
 [b41470.cmd_4907]
 RelativePath=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b41470\b41470\b41470.cmd
@@ -33709,7 +33709,7 @@ RelativePath=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b41621\b41621\b41621.cmd
 WorkingDir=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b41621\b41621
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;JIT;EXPECTED_FAIL;REL_PASS;ISSUE_2989
+Categories=Pri0;JIT;EXPECTED_PASS
 HostStyle=0
 [b41627.cmd_4911]
 RelativePath=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b41627\b41627\b41627.cmd
@@ -34115,7 +34115,7 @@ RelativePath=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b46867\b46867\b46867.cmd
 WorkingDir=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b46867\b46867
 Expected=0
 MaxAllowedDurationSeconds=600
-Categories=Pri0;JIT;EXPECTED_FAIL;ISSUE_2989
+Categories=Pri0;JIT;EXPECTED_PASS
 HostStyle=0
 [b46897.cmd_4969]
 RelativePath=JIT\Regression\CLR-x86-JIT\V1-M11-Beta1\b46897\b46897\b46897.cmd