define i32 @abs_canonical_5(i8 %x) {
; CHECK-LABEL: @abs_canonical_5(
-; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[CONV]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
;
%cmp = icmp sgt i8 %x, 0
%conv = sext i8 %x to i32
define i32 @nabs_canonical_5(i8 %x) {
; CHECK-LABEL: @nabs_canonical_5(
-; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[CONV]], i1 false)
-; CHECK-NEXT: [[ABS:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[ABS:%.*]] = sub nsw i32 0, [[TMP2]]
; CHECK-NEXT: ret i32 [[ABS]]
;
%cmp = icmp sgt i8 %x, 0
; sign bits, the abs reduces this to 2 sign bits.
define i32 @abs_signbits(i30 %x) {
; CHECK-LABEL: @abs_signbits(
-; CHECK-NEXT: [[EXT:%.*]] = sext i30 [[X:%.*]] to i32
-; CHECK-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[EXT]], i1 false)
-; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[ABS]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = call i30 @llvm.abs.i30(i30 [[X:%.*]], i1 false)
+; CHECK-NEXT: [[NARROW:%.*]] = add nuw i30 [[TMP1]], 1
+; CHECK-NEXT: [[ADD:%.*]] = zext i30 [[NARROW]] to i32
; CHECK-NEXT: ret i32 [[ADD]]
;
%ext = sext i30 %x to i32
define <4 x i32> @abs_signbits_vec(<4 x i30> %x) {
; CHECK-LABEL: @abs_signbits_vec(
-; CHECK-NEXT: [[EXT:%.*]] = sext <4 x i30> [[X:%.*]] to <4 x i32>
-; CHECK-NEXT: [[ABS:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[EXT]], i1 false)
-; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <4 x i32> [[ABS]], <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i30> @llvm.abs.v4i30(<4 x i30> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[NARROW:%.*]] = add nuw <4 x i30> [[TMP1]], <i30 1, i30 1, i30 1, i30 1>
+; CHECK-NEXT: [[ADD:%.*]] = zext <4 x i30> [[NARROW]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[ADD]]
;
%ext = sext <4 x i30> %x to <4 x i32>
define i32 @abs_sext(i8 %x) {
; CHECK-LABEL: @abs_sext(
-; CHECK-NEXT: [[S:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.abs.i32(i32 [[S]], i1 false)
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT: [[A:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[A]]
;
%s = sext i8 %x to i32
define <3 x i82> @abs_nsw_sext(<3 x i7> %x) {
; CHECK-LABEL: @abs_nsw_sext(
-; CHECK-NEXT: [[S:%.*]] = sext <3 x i7> [[X:%.*]] to <3 x i82>
-; CHECK-NEXT: [[A:%.*]] = call <3 x i82> @llvm.abs.v3i82(<3 x i82> [[S]], i1 true)
+; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i7> @llvm.abs.v3i7(<3 x i7> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[A:%.*]] = zext <3 x i7> [[TMP1]] to <3 x i82>
; CHECK-NEXT: ret <3 x i82> [[A]]
;
%s = sext <3 x i7> %x to <3 x i82>
define i8 @trunc_abs_sext(i8 %x) {
; CHECK-LABEL: @trunc_abs_sext(
-; CHECK-NEXT: [[S:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[A:%.*]] = tail call i32 @llvm.abs.i32(i32 [[S]], i1 true)
-; CHECK-NEXT: [[T:%.*]] = trunc i32 [[A]] to i8
-; CHECK-NEXT: ret i8 [[T]]
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT: ret i8 [[TMP1]]
;
%s = sext i8 %x to i32
%a = tail call i32 @llvm.abs.i32(i32 %s, i1 true)
define <4 x i8> @trunc_abs_sext_vec(<4 x i8> %x) {
; CHECK-LABEL: @trunc_abs_sext_vec(
-; CHECK-NEXT: [[S:%.*]] = sext <4 x i8> [[X:%.*]] to <4 x i32>
-; CHECK-NEXT: [[A:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[S]], i1 true)
-; CHECK-NEXT: [[T:%.*]] = trunc <4 x i32> [[A]] to <4 x i8>
-; CHECK-NEXT: ret <4 x i8> [[T]]
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT: ret <4 x i8> [[TMP1]]
;
%s = sext <4 x i8> %x to <4 x i32>
%a = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> %s, i1 true)