Instruction *InstCombiner::foldICmpTruncConstant(ICmpInst &Cmp,
Instruction *Trunc,
const APInt *C) {
- // FIXME: This check restricts all folds under here to scalar types.
- ConstantInt *RHS = dyn_cast<ConstantInt>(Cmp.getOperand(1));
- if (!RHS)
- return nullptr;
-
ICmpInst::Predicate Pred = Cmp.getPredicate();
Value *X = Trunc->getOperand(0);
- if (RHS->isOne() && C->getBitWidth() > 1) {
+ if (*C == 1 && C->getBitWidth() > 1) {
// icmp slt trunc(signum(V)) 1 --> icmp slt V, 1
Value *V = nullptr;
if (Pred == ICmpInst::ICMP_SLT && match(X, m_Signum(m_Value(V))))
if (Cmp.isEquality() && Trunc->hasOneUse()) {
// Simplify icmp eq (trunc x to i8), 42 -> icmp eq x, 42|highbits if all
// of the high bits truncated out of x are known.
- unsigned DstBits = Trunc->getType()->getPrimitiveSizeInBits(),
- SrcBits = X->getType()->getPrimitiveSizeInBits();
+ unsigned DstBits = Trunc->getType()->getScalarSizeInBits(),
+ SrcBits = X->getType()->getScalarSizeInBits();
APInt KnownZero(SrcBits, 0), KnownOne(SrcBits, 0);
computeKnownBits(X, KnownZero, KnownOne, 0, &Cmp);
// Pull in the high bits from known-ones set.
APInt NewRHS = C->zext(SrcBits);
NewRHS |= KnownOne & APInt::getHighBitsSet(SrcBits, SrcBits - DstBits);
- return new ICmpInst(Pred, X, Builder->getInt(NewRHS));
+ return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), NewRHS));
}
}
ret i1 %D
}
-; FIXME: Vectors should fold too...or not?
+; FIXME: Vectors should fold too...or not?
; Does this depend on the whether the source/dest types of the trunc are legal in the data layout?
define <2 x i1> @test31vec(<2 x i64> %A) {
; CHECK-LABEL: @test31vec(
ret i1 %d
}
-; FIXME: Vectors should fold too.
+; FIXME: The trunc is removed, but the icmp+lshr fold is missing.
define <2 x i1> @test36vec(<2 x i32> %a) {
; CHECK-LABEL: @test36vec(
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i32> %a, <i32 31, i32 31>
-; CHECK-NEXT: [[C:%.*]] = trunc <2 x i32> [[B]] to <2 x i8>
-; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i8> [[C]], zeroinitializer
+; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i32> [[B]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[D]]
;
%b = lshr <2 x i32> %a, <i32 31, i32 31>
ret i1 %c
}
-; FIXME: Vectors should fold too.
define <2 x i1> @test4c_vec(<2 x i64> %a) {
; CHECK-LABEL: @test4c_vec(
-; CHECK-NEXT: [[L:%.*]] = ashr <2 x i64> %a, <i64 63, i64 63>
-; CHECK-NEXT: [[NA:%.*]] = sub <2 x i64> zeroinitializer, %a
-; CHECK-NEXT: [[R:%.*]] = lshr <2 x i64> [[NA]], <i64 63, i64 63>
-; CHECK-NEXT: [[SIGNUM:%.*]] = or <2 x i64> [[L]], [[R]]
-; CHECK-NEXT: [[SIGNUM_TRUNC:%.*]] = trunc <2 x i64> [[SIGNUM]] to <2 x i32>
-; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[SIGNUM_TRUNC]], <i32 1, i32 1>
+; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> %a, <i64 1, i64 1>
; CHECK-NEXT: ret <2 x i1> [[C]]
;
%l = ashr <2 x i64> %a, <i64 63, i64 63>