ARM: tegra: Add reset GPIO information to PHY DT node

As reset GPIO information is PHY specific detail, adding
it to PHY DT node.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
index 84a4c12..6bdaba2 100644 (file)
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -7,6 +7,9 @@ Required properties :
  - reg : Address and length of the register set for the USB PHY interface.
  - phy_type : Should be one of "ulpi" or "utmi".
 
+Required properties for phy_type == ulpi:
+  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
+
 Optional properties:
   - nvidia,has-legacy-mode : boolean indicates whether this controller can
     operate in legacy mode (as APX 2500 / 2600). In legacy mode some

diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 43eb72a..2b41697 100644 (file)
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -432,6 +432,10 @@
                status = "okay";
        };
 
+       usb-phy@c5004400 {
+               nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+       };
+
        sdhci@c8000200 {
                status = "okay";
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */

diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index a965fe9..11b30db 100644 (file)
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -420,6 +420,10 @@
                status = "okay";
        };
 
+       usb-phy@c5004400 {
+               nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+       };
+
        sdhci@c8000000 {
                status = "okay";
                cd-gpios = <&gpio 173 0>; /* gpio PV5 */

diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 4204598..607bf0c 100644 (file)
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -561,6 +561,10 @@
                status = "okay";
        };
 
+       usb-phy@c5004400 {
+               nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+       };
+
        sdhci@c8000000 {
                status = "okay";
                power-gpios = <&gpio 86 0>; /* gpio PK6 */

diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index b70b4cb..e47cf6a 100644 (file)
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -310,6 +310,10 @@
                status = "okay";
        };
 
+       usb-phy@c5004400 {
+               nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+       };
+
        sdhci@c8000000 {
                status = "okay";
                bus-width = <4>;

diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index adc4754..f6c61d1 100644 (file)
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -497,6 +497,10 @@
                status = "okay";
        };
 
+       usb-phy@c5004400 {
+               nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+       };
+
        sdhci@c8000000 {
                status = "okay";
                power-gpios = <&gpio 86 0>; /* gpio PK6 */