compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
- //clocks = <&scpi_dvfs 0>;
- //clock-names = "cpu-cluster.0";
//cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&clkc CLKID_CPU_CLK>,
+ <&clkc CLKID_CPU_FCLK_P>,
+ <&clkc CLKID_SYS_PLL>;
+ clock-names = "core_clk",
+ "low_freq_clk_parent",
+ "high_freq_clk_parent";
+ operating-points-v2 = <&cpu_opp_table0>;
+ cpu-supply = <&vddcpu0>;
+ voltage-tolerance = <0>;
};
CPU1:cpu@1 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
- //clocks = <&scpi_dvfs 0>;
- //clock-names = "cpu-cluster.0";
//cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&clkc CLKID_CPU_CLK>,
+ <&clkc CLKID_CPU_FCLK_P>,
+ <&clkc CLKID_SYS_PLL>;
+ clock-names = "core_clk",
+ "low_freq_clk_parent",
+ "high_freq_clk_parent";
+ operating-points-v2 = <&cpu_opp_table0>;
+ cpu-supply = <&vddcpu0>;
+ voltage-tolerance = <0>;
};
CPU2:cpu@2 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
- //clocks = <&scpi_dvfs 0>;
- //clock-names = "cpu-cluster.0";
//cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&clkc CLKID_CPU_CLK>,
+ <&clkc CLKID_CPU_FCLK_P>,
+ <&clkc CLKID_SYS_PLL>;
+ clock-names = "core_clk",
+ "low_freq_clk_parent",
+ "high_freq_clk_parent";
+ operating-points-v2 = <&cpu_opp_table0>;
+ cpu-supply = <&vddcpu0>;
+ voltage-tolerance = <0>;
};
CPU3:cpu@3 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
- //clocks = <&scpi_dvfs 0>;
- //clock-names = "cpu-cluster.0";
//cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&clkc CLKID_CPU_CLK>,
+ <&clkc CLKID_CPU_FCLK_P>,
+ <&clkc CLKID_SYS_PLL>;
+ clock-names = "core_clk",
+ "low_freq_clk_parent",
+ "high_freq_clk_parent";
+ operating-points-v2 = <&cpu_opp_table0>;
+ cpu-supply = <&vddcpu0>;
+ voltage-tolerance = <0>;
};
idle-states {
};
};
+ cpu_opp_table0: cpu_opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <761000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <781000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <801000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <667000000>;
+ opp-microvolt = <851000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <881000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <891000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1398000000>;
+ opp-microvolt = <981000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <991000>;
+ clock-latency-ns = <2000000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1001000>;
+ clock-latency-ns = <2000000>;
+ };
+
+ opp09 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1011000>;
+ clock-latency-ns = <2000000>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 0xff08>,
function = "uart_ao_b";
};
};
+ pwmcpu_pins:pwmcpus {
+ mux {
+ groups = "pwm_ao_d_e";
+ function = "pwm_ao_d";
+ };
+ };
};
&pinctrl_periphs {