config HIGHPTE
bool "Allocate 2nd-level pagetables from highmem"
depends on HIGHMEM
+ +++ help
+ +++ The VM uses one page of physical memory for each page table.
+ +++ For systems with a lot of processes, this can use a lot of
+ +++ precious low memory, eventually leading to low memory being
+ +++ consumed by page tables. Setting this option will allow
+ +++ user-space 2nd level page tables to reside in high memory.
+ ++
++++ config CPU_SW_DOMAIN_PAN
++++ bool "Enable use of CPU domains to implement privileged no-access"
++++ depends on MMU && !ARM_LPAE
++++ default y
++++ help
++++ Increase kernel security by ensuring that normal kernel accesses
++++ are unable to access userspace addresses. This can help prevent
++++ use-after-free bugs becoming an exploitable privilege escalation
++++ by ensuring that magic values (such as LIST_POISON) will always
++++ fault when dereferenced.
++++
++++ CPUs with low-vector mappings use a best-efforts implementation.
++++ Their lower 1MB needs to remain accessible for the vectors, but
++++ the remainder of userspace will become appropriately inaccessible.
+
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
depends on PERF_EVENTS
case 8: __put_user_asm_dword(__pu_val, __pu_addr, err); break; \
default: __put_user_bad(); \
} \
++++ uaccess_restore(__ua_flags); \
} while (0)
----#define __put_user_asm_byte(x, __pu_addr, err) \
++++#define __put_user_asm(x, __pu_addr, err, instr) \
__asm__ __volatile__( \
---- "1: " TUSER(strb) " %1,[%2],#0\n" \
++++ "1: " TUSER(instr) " %1, [%2], #0\n" \
"2:\n" \
" .pushsection .text.fixup,\"ax\"\n" \
" .align 2\n" \