unsigned Opc = Is32Bit ? AArch64::CSELWr : AArch64::CSELXr;
bool Optimized = false;
auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI,
- &Optimized](Register &Reg, bool Invert) {
+ &Optimized](Register &Reg, Register &OtherReg,
+ bool Invert) {
if (Optimized)
return false;
if (mi_match(Reg, MRI, m_Neg(m_Reg(MatchReg)))) {
Opc = Is32Bit ? AArch64::CSNEGWr : AArch64::CSNEGXr;
Reg = MatchReg;
- if (Invert)
+ if (Invert) {
CC = AArch64CC::getInvertedCondCode(CC);
+ std::swap(Reg, OtherReg);
+ }
return true;
}
if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) {
Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
Reg = MatchReg;
- if (Invert)
+ if (Invert) {
CC = AArch64CC::getInvertedCondCode(CC);
+ std::swap(Reg, OtherReg);
+ }
return true;
}
if (mi_match(Reg, MRI, m_GAdd(m_Reg(MatchReg), m_SpecificICst(1)))) {
Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
Reg = MatchReg;
- if (Invert)
+ if (Invert) {
CC = AArch64CC::getInvertedCondCode(CC);
+ std::swap(Reg, OtherReg);
+ }
return true;
}
return false;
};
- Optimized |= TryFoldBinOpIntoSelect(False, /*Invert = */ false);
- Optimized |= TryFoldBinOpIntoSelect(True, /*Invert = */ true);
+ Optimized |= TryFoldBinOpIntoSelect(False, True, /*Invert = */ false);
+ Optimized |= TryFoldBinOpIntoSelect(True, False, /*Invert = */ true);
Optimized |= TryOptSelectCst();
auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC);
constrainSelectedInstRegOperands(*SelectInst, TII, TRI, RBI);
; CHECK: %reg1:gpr32 = COPY $w1
; CHECK: %f:gpr32 = COPY $w2
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSNEGWr %reg1, %f, 0, implicit $nzcv
+ ; CHECK: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
; CHECK: $w0 = COPY %select
; CHECK: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
; CHECK: %reg1:gpr32 = COPY $w1
; CHECK: %f:gpr32 = COPY $w2
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINVWr %reg1, %f, 0, implicit $nzcv
+ ; CHECK: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
; CHECK: $w0 = COPY %select
; CHECK: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
; CHECK: %reg1:gpr32 = COPY $w1
; CHECK: %f:gpr32 = COPY $w2
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %reg1, %f, 0, implicit $nzcv
+ ; CHECK: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
; CHECK: $w0 = COPY %select
; CHECK: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0