LOCAL / usb: dwc_otg: remove build warnings
authorSeung-Woo Kim <sw0312.kim@samsung.com>
Wed, 13 Sep 2017 12:29:31 +0000 (21:29 +0900)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Thu, 30 Aug 2018 05:42:38 +0000 (14:42 +0900)
There are build warnings for unused variable and casting from
pointer to integer of different size. Remove the build warnings.

NOTE: dwc_otg is not fully consider 64bit architecture and it
stores pointer into uint32_t variable already. This patch just
remove warnings for the converting.

Change-Id: I4182041881dbd3002f331a006e2b70a26e0b10c5
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
drivers/usb/host/dwc_otg/dwc_otg_driver.c
drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
drivers/usb/host/dwc_otg/dwc_otg_hcd.c
drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c

index 673231e17351e8b95f53bb076ae724fb210d8e7c..9ab59843541da144300e9ec66c450dea3fd92697 100644 (file)
@@ -837,8 +837,8 @@ static int dwc_otg_driver_probe(
                retval = -ENOMEM;
                goto fail;
        }
-       dev_info(&_dev->dev, "base=0x%08x\n",
-                (unsigned)dwc_otg_device->os_dep.base);
+       dev_info(&_dev->dev, "base=%p\n",
+                dwc_otg_device->os_dep.base);
 #endif
 
        /*
index ca362db1602aa935ae48ab89fc740859f72d83cd..28b4fce1efe6176f18c2e3db6b79d0b87707051f 100644 (file)
@@ -301,7 +301,7 @@ static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, i
                last = 1;
 
        /* New DMA address - address of bounce buffer referred to in index */
-       hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
+       hcdma.d32 = (uint32_t)(uintptr_t) &blob->channel[n].index[i].buf[0];
        //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
        //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
        fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
@@ -1347,7 +1347,7 @@ void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
        /* We got an interrupt, didn't handle it. */
        if (kick_irq) {
                state->mphi_int_count++;
-               FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+               FIQ_WRITE(state->mphi_regs.outdda, (unsigned int)(uintptr_t) state->dummy_send);
                FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
 
        }
@@ -1408,7 +1408,7 @@ void notrace dwc_otg_fiq_nop(struct fiq_state *state)
                FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
                /* Force a clear before another dummy send */
                FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
-               FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+               FIQ_WRITE(state->mphi_regs.outdda, (unsigned int)(uintptr_t) state->dummy_send);
                FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
 
        }
index e59747cee7ab9f7d4d858283869bd37ca78d7932..f158e6ae8534256951cf66d684002da1165edb04 100644 (file)
@@ -1041,9 +1041,9 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
                 * moderately readable array casts.
                 */
                hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
-               DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
-                               (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
-                               sizeof(struct fiq_dma_channel) * num_channels);
+               DWC_WARN("FIQ DMA bounce buffers: virt = %p dma = %pad len=%u",
+                               hcd->fiq_dmab, &hcd->fiq_state->dma_base,
+                               (uint32_t)sizeof(struct fiq_dma_channel) * num_channels);
 
                DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
 
@@ -1524,7 +1524,7 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st,
                 * state depending on transaction progress.
                 */
                blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-               st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
+               st->hcdma_copy.d32 = (uint32_t)(uintptr_t) &blob->channel[hc->hc_num].index[0].buf[0];
                /* Calculate the max number of CSPLITS such that the FIQ can time out
                 * a transaction if it fails.
                 */
@@ -1573,7 +1573,7 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st,
                        ptr = qtd->urb->buf + frame_desc->offset;
                        /* Point the HC at the DMA address of the bounce buffers */
                        blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-                       st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
+                       st->hcdma_copy.d32 = (uint32_t)(uintptr_t) &blob->channel[hc->hc_num].index[0].buf[0];
 
                        /* fixup xfersize to the actual packet size */
                        st->hctsiz_copy.b.pid = 0;
index 6947e98b87adb6a5002127215943ad1ac126a05f..c7c1e5731f5ebd95f4f1a3c8181ca2def3cb98d2 100644 (file)
@@ -948,7 +948,6 @@ static void release_channel(dwc_otg_hcd_t * hcd,
 {
        dwc_otg_transaction_type_e tr_type;
        int free_qtd;
-
        int hog_port = 0;
 
        DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d, xfer_len %d\n",
index ed9694058ed0a5f48b779e79e408d49652b234fb..dbcb9209cc841651932c85e585b649af1329ca8c 100644 (file)
@@ -483,7 +483,7 @@ static void hcd_init_fiq(void *cookie)
        dwc_otg_hcd->fiq_state->mphi_regs.outddb  = otg_dev->os_dep.mphi_base + 0x2c;
        dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
        dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
-       DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
+       DWC_WARN("MPHI regs_base at %p", dwc_otg_hcd->fiq_state->mphi_regs.base);
        //Enable mphi peripheral
        writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
 #ifdef DEBUG