flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
| (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
#else
- // FPU enable . MMU enabled . MMU no-fault . Supervisor
- flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
+ // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
+ flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
+ | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
| env->psrs;
#endif
cs_base = env->npc;
#define CMDLINE_ADDR 0x007ff000
#define INITRD_LOAD_ADDR 0x00800000
#define PROM_SIZE_MAX (256 * 1024)
-#define PROM_ADDR 0xffd00000
+#define PROM_PADDR 0xff0000000ULL
+#define PROM_VADDR 0xffd00000
#define PROM_FILENAME "openbios-sparc32"
#define MAX_CPUS 16
linux_boot = (kernel_filename != NULL);
prom_offset = RAM_size + vram_size;
- cpu_register_physical_memory(PROM_ADDR,
+ cpu_register_physical_memory(PROM_PADDR,
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
prom_offset | IO_MEM_ROM);
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
- ret = load_elf(buf, 0, NULL, NULL, NULL);
+ ret = load_elf(buf, PROM_PADDR - PROM_VADDR, NULL, NULL, NULL);
if (ret < 0) {
fprintf(stderr, "qemu: could not load prom '%s'\n",
buf);
cpu_model = "TI SuperSparc II";
sun4m_common_init(RAM_size, boot_device, ds, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model,
- 1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok
+ 1, 0xffffffff); // XXX actually first 62GB ok
}
QEMUMachine ss5_machine = {
unsigned long page_offset;
virt_addr = address & TARGET_PAGE_MASK;
+
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
+ // Boot mode: instruction fetches are taken from PROM
+ if (rw == 2 && (env->mmuregs[0] & MMU_BM)) {
+ *physical = 0xff0000000ULL | (address & 0x3ffffULL);
+ *prot = PAGE_READ | PAGE_EXEC;
+ return 0;
+ }
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return 0;
oldreg = env->mmuregs[reg];
switch(reg) {
case 0:
- env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
- env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
+ env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM);
+ env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM);
// Mappings generated during no-fault mode or MMU
// disabled mode are invalid in normal mode
if (oldreg != env->mmuregs[reg])
env->pstate = PS_PRIV;
env->pc = 0x1fff0000000ULL;
#else
- env->pc = 0xffd00000;
+ env->pc = 0;
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
+ env->mmuregs[0] |= MMU_BM;
#endif
env->npc = env->pc + 4;
#endif
env->version = def->iu_version;
env->fsr = def->fpu_version;
#if !defined(TARGET_SPARC64)
- env->mmuregs[0] = def->mmu_version;
+ env->mmuregs[0] |= def->mmu_version;
#endif
return 0;
}