drm/amd/pm: Fix output of pp_od_clk_voltage

Printing the other clock types should not be conditioned on being able
to print OD_SCLK. Some GPUs currently have limited capability of only
printing a subset of these.

Since this condition was introduced in v5.18-rc1, reading from
`pp_od_clk_voltage` has been returning empty on the Asus ROG Strix G15
(2021).

Fixes: 79c65f3fcbb1 ("drm/amd/pm: do not expose power implementation details to amdgpu_pm.c")
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Jonatas Esteves <jntesteves@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 58c2246..f4f4045 100644 (file)
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -871,13 +871,11 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
        }
        if (ret == -ENOENT) {
                size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
-               if (size > 0) {
-                       size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
-                       size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
-                       size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
-                       size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
-                       size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
-               }
+               size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
+               size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
+               size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
+               size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
+               size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
        }
 
        if (size == 0)