Signed-off-by: H. Peter Anvin <hpa@zytor.com>
prefix.vex[1] = *data++;
prefix.rex = REX_V;
- prefix.vex_c = 0;
+ prefix.vex_c = RV_VEX;
if (prefix.vex[0] == 0xc4) {
prefix.vex[2] = *data++;
prefix.vex_lp = prefix.vex[1] & 7;
}
- ix = itable_vex[0][prefix.vex_m][prefix.vex_lp];
+ ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp];
}
end_prefix = true;
break;
prefix.vex[2] = *data++;
prefix.rex = REX_V;
- prefix.vex_c = 1;
+ prefix.vex_c = RV_XOP;
prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
prefix.vex_lp = prefix.vex[2] & 7;
- ix = itable_vex[1][prefix.vex_m][prefix.vex_lp];
+ ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp];
}
end_prefix = true;
break;
#define REX_V 0x0400 /* Instruction uses VEX/XOP instead of REX */
/*
+ * REX_V "classes" (prefixes which behave like VEX)
+ */
+enum vex_class {
+ RV_VEX = 0, /* C4/C5 */
+ RV_XOP = 1 /* 8F */
+};
+
+/*
* Note that because segment registers may be used as instruction
* prefixes, we must ensure the enumerations for prefixes and
* register names do not overlap.