Handle AssertZExt in addition to AND.
}]>;
def zexti32 : ComplexPattern<i64, 1, "selectZExtBits<32>">;
def zexti16 : ComplexPattern<XLenVT, 1, "selectZExtBits<16>">;
+def zexti8 : ComplexPattern<XLenVT, 1, "selectZExtBits<8>">;
class binop_oneuse<SDPatternOperator operator>
: PatFrag<(ops node:$A, node:$B),
let Predicates = [HasStdExtZbkb] in {
def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
- (and GPR:$rs1, 0x00FF)),
+ (zexti8 GPR:$rs1)),
(PACKH GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)),
- (and GPR:$rs1, 0x00FF)),
+def : Pat<(or (shl (zexti8 GPR:$rs2), (XLenVT 8)),
+ (zexti8 GPR:$rs1)),
(PACKH GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbkb]
%or = or i64 %shl, %and
ret i64 %or
}
+
+
+define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
+; RV32I-LABEL: packh_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a1, 8
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32ZBKB-LABEL: packh_i16:
+; RV32ZBKB: # %bb.0:
+; RV32ZBKB-NEXT: packh a0, a0, a1
+; RV32ZBKB-NEXT: ret
+ %zext = zext i8 %a to i16
+ %zext1 = zext i8 %b to i16
+ %shl = shl i16 %zext1, 8
+ %or = or i16 %shl, %zext
+ ret i16 %or
+}
%or = or i64 %shl, %and
ret i64 %or
}
+
+define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
+; RV64I-LABEL: packh_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 8
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBKB-LABEL: packh_i16:
+; RV64ZBKB: # %bb.0:
+; RV64ZBKB-NEXT: packh a0, a0, a1
+; RV64ZBKB-NEXT: ret
+ %zext = zext i8 %a to i16
+ %zext1 = zext i8 %b to i16
+ %shl = shl i16 %zext1, 8
+ %or = or i16 %shl, %zext
+ ret i16 %or
+}