#define EMEV2_SCU_BASE 0x1e000000
+static DEFINE_SPINLOCK(scu_lock);
static void __iomem *scu_base;
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+ unsigned long tmp;
+
+ /* we assume this code is running on a different cpu
+ * than the one that is changing coherency setting */
+ spin_lock(&scu_lock);
+ tmp = readl(scu_base + 8);
+ tmp &= ~clr;
+ tmp |= set;
+ writel(tmp, scu_base + 8);
+ spin_unlock(&scu_lock);
+
+}
+
static unsigned int __init emev2_get_core_count(void)
{
if (!scu_base) {
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- scu_power_mode(scu_base, 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
/* Tell ROM loader about our vector (in headsmp.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu = cpu_logical_map(0);
+
scu_enable(scu_base);
/* enable cache coherency on CPU0 */
- scu_power_mode(scu_base, 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
}
static void __init emev2_smp_init_cpus(void)