drm/amdgpu: export more gpu info for gfx9

v2: 64-bit aligned for gpu info
v3: squash in wave_front_fix

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a4fc54c..c9f9357 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -967,6 +967,9 @@ struct amdgpu_gfx_config {
        unsigned mc_arb_ramcfg;
        unsigned gb_addr_config;
        unsigned num_rbs;
+       unsigned gs_vgt_table_depth;
+       unsigned gs_prim_buffer_depth;
+       unsigned max_gs_waves_per_vgt;
 
        uint32_t tile_mode_array[32];
        uint32_t macrotile_mode_array[16];
@@ -981,6 +984,7 @@ struct amdgpu_gfx_config {
 struct amdgpu_cu_info {
        uint32_t number; /* total active CU number */
        uint32_t ao_cu_mask;
+       uint32_t wave_front_size;
        uint32_t bitmap[4][4];
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 832be63..21f616c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -546,10 +546,21 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 
                if (amdgpu_ngg) {
                        dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr;
+                       dev_info.prim_buf_size = adev->gfx.ngg.buf[PRIM].size;
                        dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr;
+                       dev_info.pos_buf_size = adev->gfx.ngg.buf[POS].size;
                        dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr;
+                       dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[CNTL].size;
                        dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr;
+                       dev_info.param_buf_size = adev->gfx.ngg.buf[PARAM].size;
                }
+               dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
+               dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
+               dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+               dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
+               dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
+               dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
+               dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_waves_per_vgt;
 
                return copy_to_user(out, &dev_info,
                                    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9a9cb90..210d21c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -785,6 +785,9 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+               adev->gfx.config.gs_vgt_table_depth = 32;
+               adev->gfx.config.gs_prim_buffer_depth = 1792;
+               adev->gfx.config.max_gs_waves_per_vgt = 32;
                gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
                break;
        default:

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 95260e5..6c249e5 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -767,6 +767,25 @@ struct drm_amdgpu_info_device {
        __u64 cntl_sb_buf_gpu_addr;
        /* NGG Parameter Cache */
        __u64 param_buf_gpu_addr;
+       __u32 prim_buf_size;
+       __u32 pos_buf_size;
+       __u32 cntl_sb_buf_size;
+       __u32 param_buf_size;
+       /* wavefront size*/
+       __u32 wave_front_size;
+       /* shader visible vgprs*/
+       __u32 num_shader_visible_vgprs;
+       /* CU per shader array*/
+       __u32 num_cu_per_sh;
+       /* number of tcc blocks*/
+       __u32 num_tcc_blocks;
+       /* gs vgt table depth*/
+       __u32 gs_vgt_table_depth;
+       /* gs primitive buffer depth*/
+       __u32 gs_prim_buffer_depth;
+       /* max gs wavefront per vgt*/
+       __u32 max_gs_waves_per_vgt;
+       __u32 _pad1;
 };
 
 struct drm_amdgpu_info_hw_ip {