clk: ast2600: Add YCLK control for HACE
authorJoel Stanley <joel@jms.id.au>
Wed, 27 Oct 2021 06:17:26 +0000 (14:17 +0800)
committerTom Rini <trini@konsulko.com>
Wed, 17 Nov 2021 22:05:00 +0000 (17:05 -0500)
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
arch/arm/include/asm/arch-aspeed/scu_ast2600.h
drivers/clk/aspeed/clk_ast2600.c

index a205fb1..d7b500f 100644 (file)
@@ -10,8 +10,9 @@
 #define SCU_CLKGATE1_EMMC                      BIT(27)
 #define SCU_CLKGATE1_MAC2                      BIT(21)
 #define SCU_CLKGATE1_MAC1                      BIT(20)
-#define SCU_CLKGATE1_USB_HUB           BIT(14)
-#define SCU_CLKGATE1_USB_HOST2         BIT(7)
+#define SCU_CLKGATE1_USB_HUB                   BIT(14)
+#define SCU_CLKGATE1_HACE                      BIT(13)
+#define SCU_CLKGATE1_USB_HOST2                 BIT(7)
 
 #define SCU_CLKGATE2_FSI                       BIT(30)
 #define SCU_CLKGATE2_MAC4                      BIT(21)
index 3a92739..9871a6b 100644 (file)
@@ -1013,6 +1013,25 @@ static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu)
        return 0;
 }
 
+static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
+{
+       uint32_t reset_bit;
+       uint32_t clkgate_bit;
+
+       reset_bit = BIT(ASPEED_RESET_HACE);
+       clkgate_bit = SCU_CLKGATE1_HACE;
+
+       /*
+        * we don't do reset assertion here as HACE
+        * shares the same reset control with ACRY
+        */
+       writel(clkgate_bit, &scu->clkgate_clr1);
+       mdelay(20);
+       writel(reset_bit, &scu->modrst_clr1);
+
+       return 0;
+}
+
 static int ast2600_clk_enable(struct clk *clk)
 {
        struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@@ -1051,6 +1070,9 @@ static int ast2600_clk_enable(struct clk *clk)
        case ASPEED_CLK_GATE_USBPORT2CLK:
                ast2600_enable_usbbhclk(priv->scu);
                break;
+       case ASPEED_CLK_GATE_YCLK:
+               ast2600_enable_haceclk(priv->scu);
+               break;
        default:
                pr_err("can't enable clk\n");
                return -ENOENT;