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perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints
author
Kan Liang
<kan.liang@linux.intel.com>
Thu, 26 Aug 2021 15:32:43 +0000
(08:32 -0700)
committer
Peter Zijlstra
<peterz@infradead.org>
Tue, 31 Aug 2021 11:59:37 +0000
(13:59 +0200)
SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.
Fixes:
2a8e51eae7c8
("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link:
https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/uncore_snbep.c
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diff --git
a/arch/x86/events/intel/uncore_snbep.c
b/arch/x86/events/intel/uncore_snbep.c
index
cd53057
..
eb2c6ce
100644
(file)
--- a/
arch/x86/events/intel/uncore_snbep.c
+++ b/
arch/x86/events/intel/uncore_snbep.c
@@
-5776,6
+5776,7
@@
static struct intel_uncore_type spr_uncore_upi = {
static struct intel_uncore_type spr_uncore_m3upi = {
SPR_UNCORE_PCI_COMMON_FORMAT(),
.name = "m3upi",
+ .constraints = icx_uncore_m3upi_constraints,
};
static struct intel_uncore_type spr_uncore_mdf = {