[LoopRotate] Name instructions in test (NFC)

diff --git a/llvm/test/Transforms/LoopRotate/callbr.ll b/llvm/test/Transforms/LoopRotate/callbr.ll
index d9fbcb4..bdc415d 100644 (file)
--- a/llvm/test/Transforms/LoopRotate/callbr.ll
+++ b/llvm/test/Transforms/LoopRotate/callbr.ll
@@ -9,95 +9,97 @@
 
 define i32 @o() #0 {
 ; CHECK-LABEL: @o(
-; CHECK-NEXT:    [[TMP1:%.*]] = alloca [1 x i32], align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = load i8*, i8** bitcast (i64* @d to i8**), align 8
-; CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* @f, align 4
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
-; CHECK-NEXT:    br i1 [[TMP4]], label [[TMP17:%.*]], label [[DOTLR_PH4:%.*]]
-; CHECK:       .lr.ph4:
-; CHECK-NEXT:    br label [[TMP5:%.*]]
-; CHECK:       5:
-; CHECK-NEXT:    [[TMP6:%.*]] = phi i32 [ [[TMP3]], [[DOTLR_PH4]] ], [ [[TMP15:%.*]], [[M_EXIT:%.*]] ]
-; CHECK-NEXT:    [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 4
-; CHECK-NEXT:    [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
-; CHECK-NEXT:    store i32 [[TMP8]], i32* @g, align 4
-; CHECK-NEXT:    [[TMP9:%.*]] = bitcast [1 x i32]* [[TMP1]] to i8*
-; CHECK-NEXT:    [[TMP10:%.*]] = call i32 @n(i8* nonnull [[TMP9]], i8* [[TMP2]])
-; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
-; CHECK-NEXT:    br i1 [[TMP11]], label [[THREAD_PRE_SPLIT:%.*]], label [[DOT_CRIT_EDGE:%.*]]
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[I:%.*]] = alloca [1 x i32], align 4
+; CHECK-NEXT:    [[I1:%.*]] = load i8*, i8** bitcast (i64* @d to i8**), align 8
+; CHECK-NEXT:    [[I33:%.*]] = load i32, i32* @f, align 4
+; CHECK-NEXT:    [[I44:%.*]] = icmp eq i32 [[I33]], 0
+; CHECK-NEXT:    br i1 [[I44]], label [[BB15:%.*]], label [[BB5_LR_PH:%.*]]
+; CHECK:       bb5.lr.ph:
+; CHECK-NEXT:    br label [[BB5:%.*]]
+; CHECK:       bb5:
+; CHECK-NEXT:    [[I35:%.*]] = phi i32 [ [[I33]], [[BB5_LR_PH]] ], [ [[I3:%.*]], [[M_EXIT:%.*]] ]
+; CHECK-NEXT:    [[I6:%.*]] = icmp ult i32 [[I35]], 4
+; CHECK-NEXT:    [[I7:%.*]] = zext i1 [[I6]] to i32
+; CHECK-NEXT:    store i32 [[I7]], i32* @g, align 4
+; CHECK-NEXT:    [[I8:%.*]] = bitcast [1 x i32]* [[I]] to i8*
+; CHECK-NEXT:    [[I9:%.*]] = call i32 @n(i8* nonnull [[I8]], i8* [[I1]])
+; CHECK-NEXT:    [[I10:%.*]] = icmp eq i32 [[I9]], 0
+; CHECK-NEXT:    br i1 [[I10]], label [[THREAD_PRE_SPLIT:%.*]], label [[BB5_BB15_CRIT_EDGE:%.*]]
 ; CHECK:       thread-pre-split:
 ; CHECK-NEXT:    [[DOTPR:%.*]] = load i32, i32* @i, align 4
-; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[DOTPR]], 0
-; CHECK-NEXT:    br i1 [[TMP12]], label [[M_EXIT]], label [[DOTLR_PH:%.*]]
-; CHECK:       .lr.ph:
-; CHECK-NEXT:    br label [[TMP13:%.*]]
-; CHECK:       13:
-; CHECK-NEXT:    [[DOT11:%.*]] = phi i32 [ undef, [[DOTLR_PH]] ], [ [[TMP14:%.*]], [[J_EXIT_I:%.*]] ]
+; CHECK-NEXT:    [[I12:%.*]] = icmp eq i32 [[DOTPR]], 0
+; CHECK-NEXT:    br i1 [[I12]], label [[M_EXIT]], label [[BB13_LR_PH:%.*]]
+; CHECK:       bb13.lr.ph:
+; CHECK-NEXT:    br label [[BB13:%.*]]
+; CHECK:       bb13:
+; CHECK-NEXT:    [[DOT11:%.*]] = phi i32 [ undef, [[BB13_LR_PH]] ], [ [[I14:%.*]], [[J_EXIT_I:%.*]] ]
 ; CHECK-NEXT:    callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"() #[[ATTR1:[0-9]+]]
-; CHECK-NEXT:    to label [[J_EXIT_I]] [label %.m.exit_crit_edge]
+; CHECK-NEXT:    to label [[J_EXIT_I]] [label %bb13.m.exit_crit_edge]
 ; CHECK:       j.exit.i:
-; CHECK-NEXT:    [[TMP14]] = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #[[ATTR2:[0-9]+]]
-; CHECK-NEXT:    br i1 [[TMP12]], label [[DOTM_EXIT_CRIT_EDGE2:%.*]], label [[TMP13]]
-; CHECK:       .m.exit_crit_edge:
-; CHECK-NEXT:    [[SPLIT:%.*]] = phi i32 [ [[DOT11]], [[TMP13]] ]
+; CHECK-NEXT:    [[I14]] = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #[[ATTR2:[0-9]+]]
+; CHECK-NEXT:    br i1 [[I12]], label [[BB11_M_EXIT_CRIT_EDGE:%.*]], label [[BB13]]
+; CHECK:       bb13.m.exit_crit_edge:
+; CHECK-NEXT:    [[SPLIT:%.*]] = phi i32 [ [[DOT11]], [[BB13]] ]
 ; CHECK-NEXT:    br label [[M_EXIT]]
-; CHECK:       .m.exit_crit_edge2:
-; CHECK-NEXT:    [[SPLIT3:%.*]] = phi i32 [ [[TMP14]], [[J_EXIT_I]] ]
+; CHECK:       bb11.m.exit_crit_edge:
+; CHECK-NEXT:    [[SPLIT2:%.*]] = phi i32 [ [[I14]], [[J_EXIT_I]] ]
 ; CHECK-NEXT:    br label [[M_EXIT]]
 ; CHECK:       m.exit:
-; CHECK-NEXT:    [[DOT1_LCSSA:%.*]] = phi i32 [ [[SPLIT]], [[DOTM_EXIT_CRIT_EDGE:%.*]] ], [ [[SPLIT3]], [[DOTM_EXIT_CRIT_EDGE2]] ], [ undef, [[THREAD_PRE_SPLIT]] ]
+; CHECK-NEXT:    [[DOT1_LCSSA:%.*]] = phi i32 [ [[SPLIT]], [[BB13_M_EXIT_CRIT_EDGE:%.*]] ], [ [[SPLIT2]], [[BB11_M_EXIT_CRIT_EDGE]] ], [ undef, [[THREAD_PRE_SPLIT]] ]
 ; CHECK-NEXT:    store i32 [[DOT1_LCSSA]], i32* @h, align 4
-; CHECK-NEXT:    [[TMP15]] = load i32, i32* @f, align 4
-; CHECK-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
-; CHECK-NEXT:    br i1 [[TMP16]], label [[DOT_CRIT_EDGE5:%.*]], label [[TMP5]]
-; CHECK:       ._crit_edge:
-; CHECK-NEXT:    br label [[TMP17]]
-; CHECK:       ._crit_edge5:
-; CHECK-NEXT:    br label [[TMP17]]
-; CHECK:       17:
+; CHECK-NEXT:    [[I3]] = load i32, i32* @f, align 4
+; CHECK-NEXT:    [[I4:%.*]] = icmp eq i32 [[I3]], 0
+; CHECK-NEXT:    br i1 [[I4]], label [[BB2_BB15_CRIT_EDGE:%.*]], label [[BB5]]
+; CHECK:       bb5.bb15_crit_edge:
+; CHECK-NEXT:    br label [[BB15]]
+; CHECK:       bb2.bb15_crit_edge:
+; CHECK-NEXT:    br label [[BB15]]
+; CHECK:       bb15:
 ; CHECK-NEXT:    ret i32 undef
 ;
-  %1 = alloca [1 x i32], align 4
-  %2 = load i8*, i8** bitcast (i64* @d to i8**), align 8
-  br label %3
+bb:
+  %i = alloca [1 x i32], align 4
+  %i1 = load i8*, i8** bitcast (i64* @d to i8**), align 8
+  br label %bb2
 
-; <label>:3:                                      ; preds = %m.exit, %0
-  %4 = load i32, i32* @f, align 4
-  %5 = icmp eq i32 %4, 0
-  br i1 %5, label %16, label %6
+bb2:                                              ; preds = %m.exit, %bb
+  %i3 = load i32, i32* @f, align 4
+  %i4 = icmp eq i32 %i3, 0
+  br i1 %i4, label %bb15, label %bb5
 
-; <label>:6:                                      ; preds = %3
-  %7 = icmp ult i32 %4, 4
-  %8 = zext i1 %7 to i32
-  store i32 %8, i32* @g, align 4
-  %9 = bitcast [1 x i32]* %1 to i8*
-  %10 = call i32 @n(i8* nonnull %9, i8* %2)
-  %11 = icmp eq i32 %10, 0
-  br i1 %11, label %thread-pre-split, label %16
+bb5:                                              ; preds = %bb2
+  %i6 = icmp ult i32 %i3, 4
+  %i7 = zext i1 %i6 to i32
+  store i32 %i7, i32* @g, align 4
+  %i8 = bitcast [1 x i32]* %i to i8*
+  %i9 = call i32 @n(i8* nonnull %i8, i8* %i1)
+  %i10 = icmp eq i32 %i9, 0
+  br i1 %i10, label %thread-pre-split, label %bb15
 
-thread-pre-split:                                 ; preds = %6
+thread-pre-split:                                 ; preds = %bb5
   %.pr = load i32, i32* @i, align 4
-  br label %12
+  br label %bb11
 
-; <label>:12:                                     ; preds = %j.exit.i, %thread-pre-split
-  %.1 = phi i32 [ %15, %j.exit.i ], [ undef, %thread-pre-split ]
-  %13 = icmp eq i32 %.pr, 0
-  br i1 %13, label %m.exit, label %14
+bb11:                                             ; preds = %j.exit.i, %thread-pre-split
+  %.1 = phi i32 [ %i14, %j.exit.i ], [ undef, %thread-pre-split ]
+  %i12 = icmp eq i32 %.pr, 0
+  br i1 %i12, label %m.exit, label %bb13
 
-; <label>:14:                                     ; preds = %12
+bb13:                                             ; preds = %bb11
   callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"() #1
   to label %j.exit.i [label %m.exit]
 
-j.exit.i:                                         ; preds = %14
-  %15 = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #2
-  br label %12
+j.exit.i:                                         ; preds = %bb13
+  %i14 = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #2
+  br label %bb11
 
-m.exit:                                           ; preds = %14, %12
-  %.1.lcssa = phi i32 [ %.1, %14 ], [ %.1, %12 ]
+m.exit:                                           ; preds = %bb13, %bb11
+  %.1.lcssa = phi i32 [ %.1, %bb13 ], [ %.1, %bb11 ]
   store i32 %.1.lcssa, i32* @h, align 4
-  br label %3
+  br label %bb2
 
-; <label>:16:                                     ; preds = %6, %3
+bb15:                                             ; preds = %bb5, %bb2
   ret i32 undef
 }