clk: samsung: exynos5433: Update definitions of ISP, CAM{0,1} domain clocks

This patch adds CLK_IS_CRITICAL and CLK_IGNORE_UNUSED flags to some camera
subsystem clocks to keep them always enabled, until handling of these clocks
is added to the driver.

Change-Id: I8db5d90b21d59e20a6b8461021fac68b0ddfa780
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 632bdd0..1965273 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -583,16 +583,16 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
                        ENABLE_ACLK_TOP, 13,
-                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
                        ENABLE_ACLK_TOP, 12,
                        CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
                        ENABLE_ACLK_TOP, 11,
-                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
                        ENABLE_ACLK_TOP, 10,
-                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
                        ENABLE_ACLK_TOP, 9,
                        CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
@@ -601,7 +601,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
                        CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
                        ENABLE_ACLK_TOP, 7,
-                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
                        ENABLE_ACLK_TOP, 6,
                        CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
@@ -624,11 +624,11 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
 
        /* ENABLE_SCLK_TOP_CAM1 */
        GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
-                       ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
+                       ENABLE_SCLK_TOP_CAM1, 7, CLK_IS_CRITICAL, 0),
        GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
                        ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
        GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
-                       ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
+                       ENABLE_SCLK_TOP_CAM1, 5, CLK_IS_CRITICAL, 0),
        GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
                        ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
        GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
@@ -636,7 +636,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
        GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
                        ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
        GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
-                       ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
+                       ENABLE_SCLK_TOP_CAM1, 0, CLK_IS_CRITICAL, 0),
 
        /* ENABLE_SCLK_TOP_DISP */
        GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
@@ -1655,11 +1655,12 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
        GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
                        ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
-                       ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 20,
+                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
                        19, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
-                       18, CLK_SET_RATE_PARENT, 0),
+                       18, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
                        17, 0, 0),
        GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
@@ -1668,9 +1669,11 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
        GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
                        ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
-                       ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 12,
+                       CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
-                       ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 11,
+                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
                        "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
@@ -1683,9 +1686,9 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
        GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
                        5, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
-                       4, CLK_SET_RATE_PARENT, 0),
+                       4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
-                       3, CLK_SET_RATE_PARENT, 0),
+                       3, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
                        ENABLE_SCLK_PERIC, 2,
                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
@@ -4391,17 +4394,17 @@ static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
        GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
                        ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
-                       ENABLE_ACLK_ISP0, 5, 0, 0),
+                       ENABLE_ACLK_ISP0, 5, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
-                       ENABLE_ACLK_ISP0, 4, 0, 0),
+                       ENABLE_ACLK_ISP0, 4, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
-                       ENABLE_ACLK_ISP0, 3, 0, 0),
+                       ENABLE_ACLK_ISP0, 3, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
-                       ENABLE_ACLK_ISP0, 2, 0, 0),
+                       ENABLE_ACLK_ISP0, 2, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
-                       ENABLE_ACLK_ISP0, 1, 0, 0),
+                       ENABLE_ACLK_ISP0, 1, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
-                       ENABLE_ACLK_ISP0, 0, 0, 0),
+                       ENABLE_ACLK_ISP0, 0, CLK_IGNORE_UNUSED, 0),
 
        /* ENABLE_ACLK_ISP1 */
        GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
@@ -4854,19 +4857,19 @@ static const struct samsung_div_clock cam0_div_clks[] __initconst = {
 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
        /* ENABLE_ACLK_CAM00 */
        GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
-                       6, 0, 0),
+                       6, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
-                       5, 0, 0),
+                       5, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
-                       4, 0, 0),
+                       4, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
-                       3, 0, 0),
+                       3, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
-                       ENABLE_ACLK_CAM00, 2, 0, 0),
+                       ENABLE_ACLK_CAM00, 2, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
-                       ENABLE_ACLK_CAM00, 1, 0, 0),
+                       ENABLE_ACLK_CAM00, 1, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
-                       ENABLE_ACLK_CAM00, 0, 0, 0),
+                       ENABLE_ACLK_CAM00, 0, CLK_IGNORE_UNUSED, 0),
 
        /* ENABLE_ACLK_CAM01 */
        GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
@@ -5035,27 +5038,31 @@ static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
        /* ENABLE_SCLK_CAM0 */
        GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
                        "mout_phyclk_rxbyteclkhs0_s4_user",
-                       ENABLE_SCLK_CAM0, 8, 0, 0),
+                       ENABLE_SCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
                        "mout_phyclk_rxbyteclkhs0_s2a_user",
-                       ENABLE_SCLK_CAM0, 7, 0, 0),
+                       ENABLE_SCLK_CAM0, 7, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
-                       "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
+                       "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6,
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
-                       "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
+                       "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5,
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
-                       "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
+                       "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4,
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
-                       "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
+                       "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3,
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
                        "div_sclk_pixelasync_lite_c",
-                       ENABLE_SCLK_CAM0, 2, 0, 0),
+                       ENABLE_SCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
                        "div_sclk_pixelasync_lite_c_init",
-                       ENABLE_SCLK_CAM0, 1, 0, 0),
+                       ENABLE_SCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
                        "div_sclk_pixelasync_lite_c",
-                       ENABLE_SCLK_CAM0, 0, 0, 0),
+                       ENABLE_SCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
 
        /* ENABLE_IP_CAM03 */
        GATE(CLK_LITE_FREECNT, "clk_lite_freecnt", "",
@@ -5279,13 +5286,13 @@ static const struct samsung_div_clock cam1_div_clks[] __initconst = {
 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
        /* ENABLE_ACLK_CAM10 */
        GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
-                       ENABLE_ACLK_CAM10, 4, 0, 0),
+                       ENABLE_ACLK_CAM10, 4, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
-                       ENABLE_ACLK_CAM10, 3, 0, 0),
+                       ENABLE_ACLK_CAM10, 3, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
-                       ENABLE_ACLK_CAM10, 1, 0, 0),
+                       ENABLE_ACLK_CAM10, 1, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
-                       ENABLE_ACLK_CAM10, 0, 0, 0),
+                       ENABLE_ACLK_CAM10, 0, CLK_IGNORE_UNUSED, 0),
 
        /* ENABLE_ACLK_CAM11 */
        GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
@@ -5459,36 +5466,36 @@ static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
 
        /* ENABLE_SCLK_CAM1 */
        GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
-                       15, 0, 0),
+                       15, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
-                       14, 0, 0),
+                       14, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
-                       13, 0, 0),
+                       13, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
-                       12, 0, 0),
+                       12, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
                        "mout_phyclk_rxbyteclkhs0_s2b_user",
-                       ENABLE_SCLK_CAM1, 11, 0, 0),
+                       ENABLE_SCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
-                       ENABLE_SCLK_CAM1, 10, 0, 0),
+                       ENABLE_SCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
-                       ENABLE_SCLK_CAM1, 9, 0, 0),
+                       ENABLE_SCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
-                       ENABLE_SCLK_CAM1, 7, 0, 0),
+                       ENABLE_SCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
-                       ENABLE_SCLK_CAM1, 6, 0, 0),
+                       ENABLE_SCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
-                       ENABLE_SCLK_CAM1, 5, 0, 0),
+                       ENABLE_SCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
-                       ENABLE_SCLK_CAM1, 4, 0, 0),
+                       ENABLE_SCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
-                       ENABLE_SCLK_CAM1, 3, 0, 0),
+                       ENABLE_SCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
-                       ENABLE_SCLK_CAM1, 2, 0, 0),
+                       ENABLE_SCLK_CAM1, 2, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
-                       ENABLE_SCLK_CAM1, 1, 0, 0),
+                       ENABLE_SCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
-                       ENABLE_SCLK_CAM1, 0, 0, 0),
+                       ENABLE_SCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
 
        /* IP_CAM12 */
        GATE(CLK_BTS_FD, "clk_bts_fd", "",