// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)),
(INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
-def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), 0)),
- (INSERT_SUBREG v4i32:$src, FPR32:$Sn, ssub)>;
def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), imm:$Immd)),
(INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
-def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), 0)),
- (INSERT_SUBREG v2i64:$src, FPR64:$Sn, dsub)>;
// bitcast of an extract
// f32 bitcast(vector_extract(v4i32 src, lane)) -> EXTRACT_SUBREG(INSvi32lane(-, 0, src, lane))
define <4 x i32> @test_vins_v4i32_0(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s0, s1
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[0], v1.s[0]
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
; CHECK-LABEL: test_vins_v2i32_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s0, s1
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[0], v1.s[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
define <2 x i64> @test_vins_v2i64_0(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov d0, d1
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[0], v1.d[0]
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64