[X86] Use CMOVNS for abs instead of CMOVGE.

CMOVGE reads SF and OF. CMOVNS only reads SF. This matches with
other recent changes to use a single flag where possible. It also
matches gcc codegen.

I believe this technically changes whether the conditioanl move happens
on INT_MIN, but for INT_MIN both registers are the same so it doesn't
matter.

Differential Revision: https://reviews.llvm.org/D111826

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 335a51c45903aa21a62d84d479f927f2a212300b..6f2055ef79fd321ce57f3b7bfd33ba95892e42ab 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -28176,7 +28176,7 @@ static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget,
     SDValue N0 = Op.getOperand(0);
     SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
                               DAG.getConstant(0, DL, VT), N0);
-    SDValue Ops[] = {N0, Neg, DAG.getTargetConstant(X86::COND_GE, DL, MVT::i8),
+    SDValue Ops[] = {N0, Neg, DAG.getTargetConstant(X86::COND_NS, DL, MVT::i8),
                      SDValue(Neg.getNode(), 1)};
     return DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
   }

diff --git a/llvm/test/CodeGen/X86/abs.ll b/llvm/test/CodeGen/X86/abs.ll
index 33677a875b3b1c9fe2ba000c5ac1970b7292b68f..c03923aa47ff5347f4c802bd6351eb96b895de05 100644 (file)
--- a/llvm/test/CodeGen/X86/abs.ll
+++ b/llvm/test/CodeGen/X86/abs.ll
@@ -50,7 +50,7 @@ define i16 @test_i16(i16 %a) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i16:
@@ -58,7 +58,7 @@ define i16 @test_i16(i16 %a) nounwind {
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negw %ax
-; X86-NEXT:    cmovlw %cx, %ax
+; X86-NEXT:    cmovsw %cx, %ax
 ; X86-NEXT:    retl
   %r = call i16 @llvm.abs.i16(i16 %a, i1 false)
   ret i16 %r
@@ -71,7 +71,7 @@ define i24 @test_i24(i24 %a) nounwind {
 ; X64-NEXT:    sarl $8, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i24:
@@ -81,7 +81,7 @@ define i24 @test_i24(i24 %a) nounwind {
 ; X86-NEXT:    sarl $8, %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    retl
   %r = call i24 @llvm.abs.i24(i24 %a, i1 false)
   ret i24 %r
@@ -92,7 +92,7 @@ define i32 @test_i32(i32 %a) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i32:
@@ -100,7 +100,7 @@ define i32 @test_i32(i32 %a) nounwind {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    retl
   %r = call i32 @llvm.abs.i32(i32 %a, i1 false)
   ret i32 %r
@@ -111,7 +111,7 @@ define i64 @test_i64(i64 %a) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i64:
@@ -178,7 +178,7 @@ define <1 x i32> @test_v1i32(<1 x i32> %a) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_v1i32:
@@ -186,7 +186,7 @@ define <1 x i32> @test_v1i32(<1 x i32> %a) nounwind {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    retl
   %r = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 false)
   ret <1 x i32> %r
@@ -212,10 +212,10 @@ define <2 x i32> @test_v2i32(<2 x i32> %a) nounwind {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %edx, %eax
+; X86-NEXT:    cmovsl %edx, %eax
 ; X86-NEXT:    movl %ecx, %edx
 ; X86-NEXT:    negl %edx
-; X86-NEXT:    cmovll %ecx, %edx
+; X86-NEXT:    cmovsl %ecx, %edx
 ; X86-NEXT:    retl
   %r = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 false)
   ret <2 x i32> %r
@@ -243,13 +243,13 @@ define <3 x i32> @test_v3i32(<3 x i32> %a) nounwind {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %edx, %eax
+; X86-NEXT:    cmovsl %edx, %eax
 ; X86-NEXT:    movl %ecx, %edx
 ; X86-NEXT:    negl %edx
-; X86-NEXT:    cmovll %ecx, %edx
+; X86-NEXT:    cmovsl %ecx, %edx
 ; X86-NEXT:    movl %esi, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %esi, %ecx
+; X86-NEXT:    cmovsl %esi, %ecx
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
   %r = call <3 x i32> @llvm.abs.v3i32(<3 x i32> %a, i1 false)
@@ -282,16 +282,16 @@ define <4 x i32> @test_v4i32(<4 x i32> %a) nounwind {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86-NEXT:    movl %ebx, %edx
 ; X86-NEXT:    negl %edx
-; X86-NEXT:    cmovll %ebx, %edx
+; X86-NEXT:    cmovsl %ebx, %edx
 ; X86-NEXT:    movl %edi, %ebx
 ; X86-NEXT:    negl %ebx
-; X86-NEXT:    cmovll %edi, %ebx
+; X86-NEXT:    cmovsl %edi, %ebx
 ; X86-NEXT:    movl %esi, %edi
 ; X86-NEXT:    negl %edi
-; X86-NEXT:    cmovll %esi, %edi
+; X86-NEXT:    cmovsl %esi, %edi
 ; X86-NEXT:    movl %ecx, %esi
 ; X86-NEXT:    negl %esi
-; X86-NEXT:    cmovll %ecx, %esi
+; X86-NEXT:    cmovsl %ecx, %esi
 ; X86-NEXT:    movl %esi, 12(%eax)
 ; X86-NEXT:    movl %edi, 8(%eax)
 ; X86-NEXT:    movl %ebx, 4(%eax)
@@ -345,32 +345,32 @@ define <8 x i32> @test_v8i32(<8 x i32> %a) nounwind {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %edx, %ecx
+; X86-NEXT:    cmovsl %edx, %ecx
 ; X86-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; X86-NEXT:    movl %esi, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %esi, %ecx
+; X86-NEXT:    cmovsl %esi, %ecx
 ; X86-NEXT:    movl %ecx, (%esp) # 4-byte Spill
 ; X86-NEXT:    movl %ebx, %esi
 ; X86-NEXT:    negl %esi
-; X86-NEXT:    cmovll %ebx, %esi
+; X86-NEXT:    cmovsl %ebx, %esi
 ; X86-NEXT:    movl %ebp, %ebx
 ; X86-NEXT:    negl %ebx
-; X86-NEXT:    cmovll %ebp, %ebx
+; X86-NEXT:    cmovsl %ebp, %ebx
 ; X86-NEXT:    movl %edi, %ebp
 ; X86-NEXT:    negl %ebp
-; X86-NEXT:    cmovll %edi, %ebp
+; X86-NEXT:    cmovsl %edi, %ebp
 ; X86-NEXT:    movl %eax, %edi
 ; X86-NEXT:    negl %edi
-; X86-NEXT:    cmovll %eax, %edi
+; X86-NEXT:    cmovsl %eax, %edi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %edx, %ecx
+; X86-NEXT:    cmovsl %edx, %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %ecx, 28(%edx)
 ; X86-NEXT:    movl %eax, 24(%edx)
@@ -421,32 +421,32 @@ define <8 x i16> @test_v8i16(<8 x i16> %a) nounwind {
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negw %cx
-; X86-NEXT:    cmovlw %dx, %cx
+; X86-NEXT:    cmovsw %dx, %cx
 ; X86-NEXT:    movw %cx, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
 ; X86-NEXT:    movl %esi, %ecx
 ; X86-NEXT:    negw %cx
-; X86-NEXT:    cmovlw %si, %cx
+; X86-NEXT:    cmovsw %si, %cx
 ; X86-NEXT:    movw %cx, (%esp) # 2-byte Spill
 ; X86-NEXT:    movl %ebx, %esi
 ; X86-NEXT:    negw %si
-; X86-NEXT:    cmovlw %bx, %si
+; X86-NEXT:    cmovsw %bx, %si
 ; X86-NEXT:    movl %ebp, %ebx
 ; X86-NEXT:    negw %bx
-; X86-NEXT:    cmovlw %bp, %bx
+; X86-NEXT:    cmovsw %bp, %bx
 ; X86-NEXT:    movl %edi, %ebp
 ; X86-NEXT:    negw %bp
-; X86-NEXT:    cmovlw %di, %bp
+; X86-NEXT:    cmovsw %di, %bp
 ; X86-NEXT:    movl %eax, %edi
 ; X86-NEXT:    negw %di
-; X86-NEXT:    cmovlw %ax, %di
+; X86-NEXT:    cmovsw %ax, %di
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negw %ax
-; X86-NEXT:    cmovlw %cx, %ax
+; X86-NEXT:    cmovsw %cx, %ax
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negw %cx
-; X86-NEXT:    cmovlw %dx, %cx
+; X86-NEXT:    cmovsw %dx, %cx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movw %cx, 14(%edx)
 ; X86-NEXT:    movw %ax, 12(%edx)

diff --git a/llvm/test/CodeGen/X86/combine-abs.ll b/llvm/test/CodeGen/X86/combine-abs.ll
index 1ad12cca4cb0603430343f147d35900ea8357d2c..fd5930217cb06e38af17ca68be5d4c806b53f243 100644 (file)
--- a/llvm/test/CodeGen/X86/combine-abs.ll
+++ b/llvm/test/CodeGen/X86/combine-abs.ll
@@ -41,7 +41,7 @@ define i32 @combine_i32_abs_abs(i32 %a) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    cmovll %edi, %eax
+; CHECK-NEXT:    cmovsl %edi, %eax
 ; CHECK-NEXT:    retq
   %n1 = sub i32 zeroinitializer, %a
   %b1 = icmp slt i32 %a, zeroinitializer

diff --git a/llvm/test/CodeGen/X86/iabs.ll b/llvm/test/CodeGen/X86/iabs.ll
index 3c32ca4be03accfb9e68e380aa9ec99215a8f6bc..a00ec41516c8378346549a4f8a74b009a6842ac0 100644 (file)
--- a/llvm/test/CodeGen/X86/iabs.ll
+++ b/llvm/test/CodeGen/X86/iabs.ll
@@ -50,14 +50,14 @@ define i16 @test_i16(i16 %a) nounwind {
 ; X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negw %ax
-; X86-CMOV-NEXT:    cmovlw %cx, %ax
+; X86-CMOV-NEXT:    cmovsw %cx, %ax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    retq
   %tmp1neg = sub i16 0, %a
   %b = icmp sgt i16 %a, -1
@@ -80,14 +80,14 @@ define i32 @test_i32(i32 %a) nounwind {
 ; X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negl %eax
-; X86-CMOV-NEXT:    cmovll %ecx, %eax
+; X86-CMOV-NEXT:    cmovsl %ecx, %eax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
   %tmp1neg = sub i32 0, %a
   %b = icmp sgt i32 %a, -1
@@ -112,7 +112,7 @@ define i64 @test_i64(i64 %a) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    retq
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1

diff --git a/llvm/test/CodeGen/X86/neg-abs.ll b/llvm/test/CodeGen/X86/neg-abs.ll
index 249ac1f72837efabf2df41118353d2aecca0b1f0..1eaa55921e93bd0b79edada9fcac59b38720e9e0 100644 (file)
--- a/llvm/test/CodeGen/X86/neg-abs.ll
+++ b/llvm/test/CodeGen/X86/neg-abs.ll
@@ -46,7 +46,7 @@ define i16 @neg_abs_i16(i16 %x) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    negl %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
@@ -69,7 +69,7 @@ define i32 @neg_abs_i32(i32 %x) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    negl %eax
 ; X64-NEXT:    retq
   %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
@@ -97,7 +97,7 @@ define i64 @neg_abs_i64(i64 %x) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    negq %rax
 ; X64-NEXT:    retq
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)

diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected
index 3c49f489a3531da854f17ac8b04f64279169ddaf..78abaf51680689933b202bb5e43c9d7fc7ffc8de 100644 (file)
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected
@@ -44,14 +44,14 @@ define i16 @test_i16(i16 %a) nounwind {
 ; X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negw %ax
-; X86-CMOV-NEXT:    cmovlw %cx, %ax
+; X86-CMOV-NEXT:    cmovsw %cx, %ax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    retq
   %tmp1neg = sub i16 0, %a
   %b = icmp sgt i16 %a, -1
@@ -74,14 +74,14 @@ define i32 @test_i32(i32 %a) nounwind {
 ; X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negl %eax
-; X86-CMOV-NEXT:    cmovll %ecx, %eax
+; X86-CMOV-NEXT:    cmovsl %ecx, %eax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
   %tmp1neg = sub i32 0, %a
   %b = icmp sgt i32 %a, -1
@@ -106,7 +106,7 @@ define i64 @test_i64(i64 %a) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    retq
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1