Merge remote branch 'anholt/drm-intel-next' into drm-linus

This merges the upstream Intel tree and fixes up numerous conflicts
due to patches merged into Linus tree later in -rc cycle.

Conflicts:
	drivers/char/agp/intel-agp.c
	drivers/gpu/drm/drm_dp_i2c_helper.c
	drivers/gpu/drm/i915/i915_irq.c
	drivers/gpu/drm/i915/i915_suspend.c

diff --cc drivers/char/agp/intel-agp.c
index 3cb56a0,37cb4e2..3767855
--- 1/drivers/char/agp/intel-agp.c
--- 2/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@@ -58,12 -58,11 +58,12 @@@
  #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
- #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB            0x0040
- #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG            0x0042
- #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB            0x0044
- #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB           0x0062
- #define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB    0x006a
- #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG            0x0046
+ #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB         0x0040
+ #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG         0x0042
+ #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB         0x0044
+ #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB        0x0062
++#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a
+ #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG         0x0046
  
  /* cover 915 and 945 variants */
  #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@@ -95,10 -94,9 +95,10 @@@
                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
-               agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
-               agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
-               agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \
-               agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB)
+               agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
+               agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
 -              agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB)
++              agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
++              agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB)
  
  extern int agp_memory_reserved;
  
@@@ -1357,10 -1361,9 +1357,10 @@@ static void intel_i965_get_gtt_range(in
        case PCI_DEVICE_ID_INTEL_G45_HB:
        case PCI_DEVICE_ID_INTEL_G41_HB:
        case PCI_DEVICE_ID_INTEL_B43_HB:
-       case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
-       case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
-       case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
-       case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB:
+       case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
+       case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
+       case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
++      case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
                *gtt_offset = *gtt_size = MB(2);
                break;
        default:
@@@ -2356,14 -2359,12 +2356,14 @@@ static const struct intel_driver_descri
            "B43", NULL, &intel_i965_driver },
        { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
            "G41", NULL, &intel_i965_driver },
-       { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
-           "IGDNG/D", NULL, &intel_i965_driver },
-       { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
-           "IGDNG/M", NULL, &intel_i965_driver },
-       { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
-           "IGDNG/MA", NULL, &intel_i965_driver },
-       { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
-           "IGDNG/MC2", NULL, &intel_i965_driver },
+       { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
+           "Ironlake/D", NULL, &intel_i965_driver },
+       { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
+           "Ironlake/M", NULL, &intel_i965_driver },
+       { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
+           "Ironlake/MA", NULL, &intel_i965_driver },
++      { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
++          "Ironlake/MC2", NULL, &intel_i965_driver },
        { 0, 0, 0, NULL, NULL, NULL }
  };
  
@@@ -2562,10 -2558,9 +2562,10 @@@ static struct pci_device_id agp_intel_p
        ID(PCI_DEVICE_ID_INTEL_G45_HB),
        ID(PCI_DEVICE_ID_INTEL_G41_HB),
        ID(PCI_DEVICE_ID_INTEL_B43_HB),
-       ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
-       ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
-       ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
-       ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB),
+       ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
+       ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
+       ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
++      ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
        { }
  };
  

diff --cc drivers/gpu/drm/drm_crtc.c
Simple merge

diff --cc drivers/gpu/drm/drm_dp_i2c_helper.c
Simple merge

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
index aa7fd82,a31c9d5..ae17c4b
--- 1/drivers/gpu/drm/i915/i915_irq.c
--- 2/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@@ -254,20 -273,16 +273,21 @@@ irqreturn_t ironlake_irq_handler(struc
  {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        int ret = IRQ_NONE;
-       u32 de_iir, gt_iir, de_ier;
-       u32 new_de_iir, new_gt_iir;
 -      u32 de_iir, gt_iir, pch_iir;
++      u32 de_iir, gt_iir, de_ier, pch_iir;
+       u32 new_de_iir, new_gt_iir, new_pch_iir;
        struct drm_i915_master_private *master_priv;
  
 +      /* disable master interrupt before clearing iir  */
 +      de_ier = I915_READ(DEIER);
 +      I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 +      (void)I915_READ(DEIER);
 +
        de_iir = I915_READ(DEIIR);
        gt_iir = I915_READ(GTIIR);
+       pch_iir = I915_READ(SDEIIR);
  
        for (;;) {
-               if (de_iir == 0 && gt_iir == 0)
+               if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
                        break;
  
                ret = IRQ_HANDLED;
@@@ -291,13 -310,20 +315,23 @@@
                        DRM_WAKEUP(&dev_priv->irq_queue);
                }
  
+               if (de_iir & DE_GSE)
+                       ironlake_opregion_gse_intr(dev);
+ 
+               /* check event from PCH */
+               if ((de_iir & DE_PCH_EVENT) &&
+                       (pch_iir & SDE_HOTPLUG_MASK)) {
+                       queue_work(dev_priv->wq, &dev_priv->hotplug_work);
+               }
+ 
                de_iir = new_de_iir;
                gt_iir = new_gt_iir;
+               pch_iir = new_pch_iir;
        }
  
 +      I915_WRITE(DEIER, de_ier);
 +      (void)I915_READ(DEIER);
 +
        return ret;
  }
  

diff --cc drivers/gpu/drm/i915/i915_suspend.c
index 6eec817,402a7eb..ab35e81
--- 1/drivers/gpu/drm/i915/i915_suspend.c
--- 2/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@@ -239,11 -239,6 +239,11 @@@ static void i915_save_modeset_reg(struc
        if (drm_core_check_feature(dev, DRIVER_MODESET))
                return;
  
-       if (IS_IGDNG(dev)) {
++      if (IS_IRONLAKE(dev)) {
 +              dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
 +              dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
 +      }
 +
        /* Pipe & plane A info */
        dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
        dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@@ -264,15 -259,10 +264,15 @@@
        dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
        dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
        dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
-       if (!IS_IGDNG(dev))
+       if (!IS_IRONLAKE(dev))
                dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
  
-       if (IS_IGDNG(dev)) {
+       if (IS_IRONLAKE(dev)) {
 +              dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
 +              dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
 +              dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
 +              dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
 +
                dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
                dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
  
@@@ -321,15 -310,10 +321,15 @@@
        dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
        dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
        dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
-       if (!IS_IGDNG(dev))
+       if (!IS_IRONLAKE(dev))
                dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
  
-       if (IS_IGDNG(dev)) {
+       if (IS_IRONLAKE(dev)) {
 +              dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
 +              dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
 +              dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
 +              dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
 +
                dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
                dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
  
@@@ -385,11 -368,6 +385,11 @@@ static void i915_restore_modeset_reg(st
                fpb1_reg = FPB1;
        }
  
-       if (IS_IGDNG(dev)) {
++      if (IS_IRONLAKE(dev)) {
 +              I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
 +              I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
 +      }
 +
        /* Pipe & plane A info */
        /* Prime the clock */
        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@@ -413,15 -391,10 +413,15 @@@
        I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
        I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
        I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
-       if (!IS_IGDNG(dev))
+       if (!IS_IRONLAKE(dev))
                I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
  
-       if (IS_IGDNG(dev)) {
+       if (IS_IRONLAKE(dev)) {
 +              I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
 +              I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
 +              I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
 +              I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 +
                I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
                I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
  
@@@ -467,7 -439,7 +467,7 @@@
        /* Actually enable it */
        I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
        DRM_UDELAY(150);
-       if (IS_I965G(dev) && !IS_IGDNG(dev))
 -      if (IS_I965G(dev))
++      if (IS_I965G(dev) && !IS_IRONLAKE(dev))
                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
        DRM_UDELAY(150);
  
@@@ -478,15 -450,10 +478,15 @@@
        I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
        I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
        I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
-       if (!IS_IGDNG(dev))
+       if (!IS_IRONLAKE(dev))
                I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
  
-       if (IS_IGDNG(dev)) {
+       if (IS_IRONLAKE(dev)) {
 +              I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
 +              I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
 +              I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
 +              I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 +
                I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
                I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
  

diff --cc drivers/gpu/drm/i915/intel_crt.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index 63424d5,632f1b4..4e7aa8b
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -33,8 -33,9 +33,9 @@@
  #include "intel_drv.h"
  #include "i915_drm.h"
  #include "i915_drv.h"
 -#include "intel_dp.h"
 +#include "drm_dp_helper.h"
  
+ 
  #define DP_LINK_STATUS_SIZE   6
  #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  
@@@ -390,69 -391,9 +391,69 @@@ intel_dp_i2c_aux_ch(struct i2c_adapter 
                                                     struct intel_dp_priv,
                                                     adapter);
        struct intel_output *intel_output = dp_priv->intel_output;
 +      uint16_t address = algo_data->address;
 +      uint8_t msg[5];
 +      uint8_t reply[2];
 +      int msg_bytes;
 +      int reply_bytes;
 +      int ret;
 +
 +      /* Set up the command byte */
 +      if (mode & MODE_I2C_READ)
 +              msg[0] = AUX_I2C_READ << 4;
 +      else
 +              msg[0] = AUX_I2C_WRITE << 4;
 +
 +      if (!(mode & MODE_I2C_STOP))
 +              msg[0] |= AUX_I2C_MOT << 4;
  
 -      return intel_dp_aux_ch(intel_output,
 -                             send, send_bytes, recv, recv_bytes);
 +      msg[1] = address >> 8;
 +      msg[2] = address;
 +
 +      switch (mode) {
 +      case MODE_I2C_WRITE:
 +              msg[3] = 0;
 +              msg[4] = write_byte;
 +              msg_bytes = 5;
 +              reply_bytes = 1;
 +              break;
 +      case MODE_I2C_READ:
 +              msg[3] = 0;
 +              msg_bytes = 4;
 +              reply_bytes = 2;
 +              break;
 +      default:
 +              msg_bytes = 3;
 +              reply_bytes = 1;
 +              break;
 +      }
 +
 +      for (;;) {
 +        ret = intel_dp_aux_ch(intel_output,
 +                              msg, msg_bytes,
 +                              reply, reply_bytes);
 +              if (ret < 0) {
-                       DRM_DEBUG("aux_ch failed %d\n", ret);
++                      DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 +                      return ret;
 +              }
 +              switch (reply[0] & AUX_I2C_REPLY_MASK) {
 +              case AUX_I2C_REPLY_ACK:
 +                      if (mode == MODE_I2C_READ) {
 +                              *read_byte = reply[1];
 +                      }
 +                      return reply_bytes - 1;
 +              case AUX_I2C_REPLY_NACK:
-                       DRM_DEBUG("aux_ch nack\n");
++                      DRM_DEBUG_KMS("aux_ch nack\n");
 +                      return -EREMOTEIO;
 +              case AUX_I2C_REPLY_DEFER:
-                       DRM_DEBUG("aux_ch defer\n");
++                      DRM_DEBUG_KMS("aux_ch defer\n");
 +                      udelay(100);
 +                      break;
 +              default:
 +                      DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 +                      return -EREMOTEIO;
 +              }
 +      }
  }
  
  static int

diff --cc include/drm/drm.h
Simple merge

diff --cc include/drm/drmP.h
Simple merge

diff --cc include/drm/drm_crtc.h
Simple merge

diff --cc include/drm/i915_drm.h
Simple merge