x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
authorBin Meng <bmeng.cn@gmail.com>
Thu, 13 Aug 2015 07:29:15 +0000 (00:29 -0700)
committerSimon Glass <sjg@chromium.org>
Wed, 26 Aug 2015 14:54:08 +0000 (07:54 -0700)
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
include/configs/bayleybay.h
include/configs/crownbay.h
include/configs/minnowmax.h
include/configs/qemu-x86.h
include/configs/x86-common.h

index d37a865..1ba2998 100644 (file)
@@ -16,7 +16,6 @@
 #define CONFIG_SYS_MONITOR_LEN         (1 << 20)
 #define CONFIG_ARCH_MISC_INIT
 
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 
index 57a9512..162f08f 100644 (file)
@@ -31,7 +31,6 @@
 #define CONFIG_PCI_IO_PHYS             CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE             0xe000
 
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 
index aeb04b9..53d86a2 100644 (file)
@@ -19,7 +19,6 @@
 
 #define CONFIG_SMSC_LPC47M
 
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 #define CONFIG_RTL8169
index 72df64e..1b544c1 100644 (file)
@@ -28,7 +28,6 @@
 #define CONFIG_PCI_IO_PHYS             CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE             0xe000
 
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_PCI_PNP
 
 #define CONFIG_STD_DEVICES_SETTINGS    "stdin=serial,vga\0" \
index 3d07cc0..217312e 100644 (file)
  * PCI configuration
  */
 #define CONFIG_PCI
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /*-----------------------------------------------------------------------
  * USB configuration