def ixlenimm : Operand<XLenVT>;
// Standalone (codegen-only) immleaf patterns.
-def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
+def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
+def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>;
// Addressing modes.
// Necessary because a frameindex can't be matched directly in a pattern.
/// Immediates
def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
-// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits.
+def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>;
def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
/// Simple arithmetic operations
define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a1, 4080
-; RV32I-NEXT: mv a1, a1
-; RV32I-NEXT: slli a2, a0, 8
-; RV32I-NEXT: and a1, a2, a1
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: lui a2, 4080
+; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: or a1, a1, a2
-; RV32I-NEXT: lui a2, 4080
-; RV32I-NEXT: mv a2, a2
-; RV32I-NEXT: slli a3, a0, 8
-; RV32I-NEXT: and a2, a3, a2
+; RV32I-NEXT: slli a2, a0, 8
+; RV32I-NEXT: lui a3, 4080
+; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4
-; RV32I-NEXT: lui a4, 4080
-; RV32I-NEXT: mv a4, a4
-; RV32I-NEXT: slli a5, a1, 8
-; RV32I-NEXT: and a5, a5, a4
+; RV32I-NEXT: slli a4, a1, 8
+; RV32I-NEXT: lui a5, 4080
+; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a1, a1, a5
+; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a2, a1, a2
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a3, a0, 8
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, 262464
-; RV32I-FPELIM-NEXT: mv a6, a0
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars)
; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a3, zero, 3
; RV32I-FPELIM-NEXT: addi a4, zero, 4
+; RV32I-FPELIM-NEXT: lui a6, 262464
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: jalr a7
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, 262464
-; RV32I-WITHFP-NEXT: mv a6, a0
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars)
; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a3, zero, 3
; RV32I-WITHFP-NEXT: addi a4, zero, 4
+; RV32I-WITHFP-NEXT: lui a6, 262464
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: jalr a7
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp)
+; RV32I-FPELIM-NEXT: lui a0, 524272
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: sw zero, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: sw zero, 28(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
-; RV32I-FPELIM-NEXT: lui a0, 524272
-; RV32I-FPELIM-NEXT: mv a0, a0
-; RV32I-FPELIM-NEXT: sw a0, 12(sp)
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars)
; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars)
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-WITHFP-NEXT: sw ra, 44(sp)
; RV32I-WITHFP-NEXT: sw s0, 40(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 48
+; RV32I-WITHFP-NEXT: lui a0, 524272
+; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
-; RV32I-WITHFP-NEXT: lui a0, 524272
-; RV32I-WITHFP-NEXT: mv a0, a0
-; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars)
; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars)
; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 9
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: lui a0, 524272
+; RV32I-FPELIM-NEXT: sw a0, 28(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
-; RV32I-FPELIM-NEXT: lui a0, 524272
-; RV32I-FPELIM-NEXT: mv a0, a0
-; RV32I-FPELIM-NEXT: sw a0, 28(sp)
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 9
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
+; RV32I-WITHFP-NEXT: lui a0, 524272
+; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
-; RV32I-WITHFP-NEXT: lui a0, 524272
-; RV32I-WITHFP-NEXT: mv a0, a0
-; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a1, 524272
-; RV32I-FPELIM-NEXT: mv a1, a1
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
; RV32I-FPELIM-NEXT: sw zero, 8(a0)
; RV32I-FPELIM-NEXT: sw zero, 4(a0)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a1, 524272
-; RV32I-WITHFP-NEXT: mv a1, a1
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: sw zero, 8(a0)
; RV32I-WITHFP-NEXT: sw zero, 4(a0)
; RV32IF-LABEL: fneg_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a1, 524288
-; RV32IF-NEXT: mv a1, a1
; RV32IF-NEXT: xor a0, a0, a1
; RV32IF-NEXT: ret
%1 = fsub float -0.0, %a
; RV32IF-LABEL: fsgnjn_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a2, 524288
-; RV32IF-NEXT: mv a2, a2
; RV32IF-NEXT: xor a1, a1, a2
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32I-LABEL: pos_i32_hi20_only:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 16
-; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: ret
ret i32 65536
}
; RV32I-LABEL: neg_i32_hi20_only:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 1048560
-; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: ret
ret i32 -65536
}
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, 261888
-; RV32I-FPELIM-NEXT: mv a3, a0
; RV32I-FPELIM-NEXT: lui a0, %hi(va1)
; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1)
+; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: addi a4, zero, 2
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: jalr a0
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, 261888
-; RV32I-WITHFP-NEXT: mv a3, a0
; RV32I-WITHFP-NEXT: lui a0, %hi(va1)
; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1)
+; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: addi a4, zero, 2
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: jalr a0
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, 261888
-; RV32I-FPELIM-NEXT: mv a3, a0
; RV32I-FPELIM-NEXT: lui a0, %hi(va2)
; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2)
+; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: jalr a0
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, 261888
-; RV32I-WITHFP-NEXT: mv a3, a0
; RV32I-WITHFP-NEXT: lui a0, %hi(va2)
; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2)
+; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: jalr a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, 261888
-; RV32I-FPELIM-NEXT: mv a2, a0
-; RV32I-FPELIM-NEXT: lui a0, 262144
-; RV32I-FPELIM-NEXT: mv a5, a0
; RV32I-FPELIM-NEXT: lui a0, %hi(va3)
; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3)
; RV32I-FPELIM-NEXT: addi a0, zero, 2
+; RV32I-FPELIM-NEXT: lui a2, 261888
+; RV32I-FPELIM-NEXT: lui a5, 262144
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: jalr a3
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, 261888
-; RV32I-WITHFP-NEXT: mv a2, a0
-; RV32I-WITHFP-NEXT: lui a0, 262144
-; RV32I-WITHFP-NEXT: mv a5, a0
; RV32I-WITHFP-NEXT: lui a0, %hi(va3)
; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3)
; RV32I-WITHFP-NEXT: addi a0, zero, 2
+; RV32I-WITHFP-NEXT: lui a2, 261888
+; RV32I-WITHFP-NEXT: lui a5, 262144
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: jalr a3