usb: r8a66597: Make CONFIG_RZA_USB default

No other platforms use this r8a66597 controller but RZ/A1,
make RZ/A1 support the default and drop all the other SoC
support to remove ifdeffery.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>

diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 8cca09f..d144b57 100644 (file)
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -70,20 +70,6 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
                }
        } while ((tmp & USBE) != USBE);
        r8a66597_bclr(r8a66597, USBE, SYSCFG0);
-#if !defined(CONFIG_RZA_USB)
-       r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
-
-       i = 0;
-       r8a66597_bset(r8a66597, XCKE, SYSCFG0);
-       do {
-               udelay(1000);
-               tmp = r8a66597_read(r8a66597, SYSCFG0);
-               if (i++ > 500) {
-                       printf("register access fail.\n");
-                       return -1;
-               }
-       } while ((tmp & SCKE) != SCKE);
-#else
        /*
         * RZ/A Only:
         * Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0
@@ -96,28 +82,18 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
        setbits(le16, R8A66597_BASE0, UPLLE);
        mdelay(1);
        r8a66597_bset(r8a66597, SUSPM, SUSPMODE0);
-#endif /* CONFIG_RZA_USB */
 
        return 0;
 }
 
 static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
 {
-#if !defined(CONFIG_RZA_USB)
-       r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
-       udelay(1);
-       r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
-       r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
-       r8a66597_bclr(r8a66597, USBE, SYSCFG0);
-#else
        r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0);
 
        clrbits(le16, R8A66597_BASE0, UPLLE);
        mdelay(1);
        r8a66597_bclr(r8a66597, USBE, SYSCFG0);
        mdelay(1);
-
-#endif
 }
 
 static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
@@ -127,10 +103,6 @@ static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
        val = port ? DRPD : DCFM | DRPD;
        r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
        r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
-
-#if !defined(CONFIG_RZA_USB)
-       r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
-#endif
 }
 
 static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
@@ -160,9 +132,6 @@ static int enable_controller(struct r8a66597 *r8a66597)
        if (ret < 0)
                return ret;
 
-#if !defined(CONFIG_RZA_USB)
-       r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG);
-#endif
        r8a66597_bset(r8a66597, USBE, SYSCFG0);
 
        r8a66597_bset(r8a66597, INTL, SOFCFG);
@@ -280,16 +249,13 @@ static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
        unsigned long setup_addr = USBREQ;
        u16 intsts1;
        int timeout = 3000;
-#if defined(CONFIG_RZA_USB)
        u16 dcpctr;
-#endif
        u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
 
        r8a66597_write(r8a66597, make_devsel(devsel) |
                                 (8 << dev->maxpacketsize), DCPMAXP);
        r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
 
-#if defined(CONFIG_RZA_USB)
        dcpctr = r8a66597_read(r8a66597, DCPCTR);
        if ((dcpctr & PID) == PID_BUF) {
                if (readw_poll_timeout(r8a66597->reg + DCPCTR, dcpctr,
@@ -298,7 +264,6 @@ static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
                        return -ETIMEDOUT;
                }
        }
-#endif
 
        for (i = 0; i < 4; i++) {
                r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr);

diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index 4859e26..1e370cd 100644 (file)
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -89,27 +89,14 @@
 #define SUSPMODE0      0x102   /* RZ/A only */
 
 /* System Configuration Control Register */
-#if !defined(CONFIG_RZA_USB)
-#define        XTAL            0xC000  /* b15-14: Crystal selection */
-#define          XTAL48         0x8000   /* 48MHz */
-#define          XTAL24         0x4000   /* 24MHz */
-#define          XTAL12         0x0000   /* 12MHz */
-#define        XCKE            0x2000  /* b13: External clock enable */
-#define        PLLC            0x0800  /* b11: PLL control */
-#define        SCKE            0x0400  /* b10: USB clock enable */
-#define        PCSDIS          0x0200  /* b9: not CS wakeup */
-#define        LPSME           0x0100  /* b8: Low power sleep mode */
-#endif
 #define        HSE             0x0080  /* b7: Hi-speed enable */
 #define        DCFM            0x0040  /* b6: Controller function select  */
 #define        DRPD            0x0020  /* b5: D+/- pull down control */
 #define        DPRPU           0x0010  /* b4: D+ pull up control */
-#if defined(CONFIG_RZA_USB)
 #define        XTAL            0x0004  /* b2: Crystal selection */
 #define          XTAL12         0x0004   /* 12MHz */
 #define          XTAL48         0x0000   /* 48MHz */
 #define        UPLLE           0x0002  /* b1: internal PLL control */
-#endif
 #define        USBE            0x0001  /* b0: USB module operation enable */
 
 /* System Configuration Status Register */
@@ -178,11 +165,7 @@
 #define        REW             0x4000  /* b14: Buffer rewind */
 #define        DCLRM           0x2000  /* b13: DMA buffer clear mode */
 #define        DREQE           0x1000  /* b12: DREQ output enable */
-#if !defined(CONFIG_RZA_USB)
-#define        MBW             0x0400  /* b10: Maximum bit width for FIFO access */
-#else
 #define        MBW             0x0800  /* b10: Maximum bit width for FIFO access */
-#endif
 #define          MBW_8          0x0000   /*  8bit */
 #define          MBW_16         0x0400   /* 16bit */
 #define          MBW_32         0x0800   /* 32bit */
@@ -427,7 +410,6 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
                                      int len)
 {
        int i;
-#if defined(CONFIG_RZA_USB)
        unsigned long fifoaddr = r8a66597->reg + offset;
        unsigned long count;
        unsigned long *p = buf;
@@ -440,13 +422,6 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
                unsigned long tmp = inl(fifoaddr);
                memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
        }
-#else
-       unsigned short *p = buf;
-
-       len = (len + 1) / 2;
-       for (i = 0; i < len; i++)
-               p[i] = inw(r8a66597->reg + offset);
-#endif
 }
 
 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
@@ -461,7 +436,6 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
 {
        int i;
        unsigned long fifoaddr = r8a66597->reg + offset;
-#if defined(CONFIG_RZA_USB)
        unsigned long count;
        unsigned char *pb;
        unsigned long *p = buf;
@@ -479,19 +453,6 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
                                outb(pb[i], fifoaddr + 3 - i);
                }
        }
-#else
-       int odd = len & 0x0001;
-       unsigned short *p = buf;
-
-       len = len / 2;
-       for (i = 0; i < len; i++)
-               outw(p[i], fifoaddr);
-
-       if (odd) {
-               unsigned char *pb = (unsigned char *)(buf + len);
-               outb(*pb, fifoaddr);
-       }
-#endif
 }
 
 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,