Reviewed By: arsenm, sameerds
Differential Revision: https://reviews.llvm.org/D134266
return Opc <= TargetOpcode::GENERIC_OP_END;
}
+ static bool isGenericAtomicRMWOpcode(unsigned Opc) {
+ return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
+ Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
+ }
+
/// Given a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL.
virtual
HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN)
+// Marker for start of Generic AtomicRMW opcodes
+HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG)
+
+// Marker for end of Generic AtomicRMW opcodes
+HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_FMIN)
+
// Generic atomic fence
HANDLE_TARGET_OPCODE(G_FENCE)