fix format error

diff --git a/src/jit/codegencommon.cpp b/src/jit/codegencommon.cpp
index a64e63d..55fc9d5 100644 (file)
--- a/src/jit/codegencommon.cpp
+++ b/src/jit/codegencommon.cpp
@@ -10584,7 +10584,7 @@ GenTreePtr CodeGen::genMakeConst(const void* cnsAddr, var_types cnsType, GenTree
 void CodeGen::genPreserveCalleeSavedFltRegs(unsigned lclFrameSize)
 {
     genVzeroupperIfNeeded(false);
-    regMaskTP regMask           = compiler->compCalleeFPRegsSavedMask;
+    regMaskTP regMask = compiler->compCalleeFPRegsSavedMask;
 
     // Only callee saved floating point registers should be in regMask
     assert((regMask & RBM_FLT_CALLEE_SAVED) == regMask);

diff --git a/src/jit/lowerxarch.cpp b/src/jit/lowerxarch.cpp
index ea87c9c..39d2980 100644 (file)
--- a/src/jit/lowerxarch.cpp
+++ b/src/jit/lowerxarch.cpp
@@ -1957,7 +1957,8 @@ void Lowering::TreeNodeInfoInitBlockStore(GenTreeBlk* blkNode)
                     // series of 16-byte loads and stores.
                     blkNode->gtLsraInfo.internalFloatCount = 1;
                     blkNode->gtLsraInfo.addInternalCandidates(l, l->internalFloatRegCandidates());
-                    // Uses XMM reg for load and store and hence check to see whether AVX instructions are used for codegen
+                    // Uses XMM reg for load and store and hence check to see whether AVX instructions are used for
+                    // codegen
                     SetContainsAVXFlags();
                 }
 
@@ -4579,7 +4580,7 @@ void Lowering::SetMulOpCounts(GenTreePtr tree)
 }
 
 //------------------------------------------------------------------------------
-// SetContainsAVXFlags: Set ContainsAVX flag when it is floating type, set 
+// SetContainsAVXFlags: Set ContainsAVX flag when it is floating type, set
 // Contains256bitAVX flag when SIMD vector size is 32 bytes
 //
 // Arguments: