drm/i915/tgl: Add gmbus gpio pin to port mapping

Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-18-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 92931dc..67743ee 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,6 +45,8 @@ enum i915_gpio {
        GPIOK,
        GPIOL,
        GPIOM,
+       GPION,
+       GPIOO,
 };
 
 /*

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 4f6a9bd..b42c79a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
        [GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
 };
 
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+       [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+       [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+       [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+       [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+       [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+       [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+       [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+       [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+       [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
                                             unsigned int pin)
 {
-       if (HAS_PCH_MCC(dev_priv))
+       if (HAS_PCH_TGP(dev_priv))
+               return &gmbus_pins_tgp[pin];
+       else if (HAS_PCH_MCC(dev_priv))
                return &gmbus_pins_mcc[pin];
        else if (HAS_PCH_ICP(dev_priv))
                return &gmbus_pins_icp[pin];
@@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
        unsigned int size;
 
-       if (HAS_PCH_MCC(dev_priv))
+       if (HAS_PCH_TGP(dev_priv))
+               size = ARRAY_SIZE(gmbus_pins_tgp);
+       else if (HAS_PCH_MCC(dev_priv))
                size = ARRAY_SIZE(gmbus_pins_mcc);
        else if (HAS_PCH_ICP(dev_priv))
                size = ARRAY_SIZE(gmbus_pins_icp);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad96c5b..62ac8a1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3254,8 +3254,10 @@ enum i915_power_well_id {
 #define   GMBUS_PIN_10_TC2_ICP 10
 #define   GMBUS_PIN_11_TC3_ICP 11
 #define   GMBUS_PIN_12_TC4_ICP 12
+#define   GMBUS_PIN_13_TC5_TGP 13
+#define   GMBUS_PIN_14_TC6_TGP 14
 
-#define   GMBUS_NUM_PINS       13 /* including 0 */
+#define   GMBUS_NUM_PINS       15 /* including 0 */
 #define GMBUS1                 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT     (1 << 31)
 #define   GMBUS_SW_RDY         (1 << 30)