some comments, function names, identation.
Reviewed here: http://reviews.llvm.org/D6527
llvm-svn: 224218
/// AVX2 allows masks for consecutive load and store for i32 and i64 elements.
/// AVX-512 architecture will also allow masks for non-consecutive memory
/// accesses.
- virtual bool isLegalPredicatedStore(Type *DataType, int Consecutive) const;
- virtual bool isLegalPredicatedLoad (Type *DataType, int Consecutive) const;
+ virtual bool isLegalMaskedStore(Type *DataType, int Consecutive) const;
+ virtual bool isLegalMaskedLoad (Type *DataType, int Consecutive) const;
/// \brief Return the cost of the scaling factor used in the addressing
/// mode represented by AM for this target, for a load/store
return PrevTTI->isLegalICmpImmediate(Imm);
}
-bool TargetTransformInfo::isLegalPredicatedLoad(Type *DataType,
- int Consecutive) const {
+bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
+ int Consecutive) const {
return false;
}
-bool TargetTransformInfo::isLegalPredicatedStore(Type *DataType,
- int Consecutive) const {
+bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
+ int Consecutive) const {
return false;
}
Type *Ty) const override;
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty) const override;
- bool isLegalPredicatedLoad (Type *DataType, int Consecutive) const override;
- bool isLegalPredicatedStore(Type *DataType, int Consecutive) const override;
+ bool isLegalMaskedLoad (Type *DataType, int Consecutive) const override;
+ bool isLegalMaskedStore(Type *DataType, int Consecutive) const override;
/// @}
};
return X86TTI::getIntImmCost(Imm, Ty);
}
-bool X86TTI::isLegalPredicatedLoad(Type *DataType, int Consecutive) const {
+bool X86TTI::isLegalMaskedLoad(Type *DataType, int Consecutive) const {
int ScalarWidth = DataType->getScalarSizeInBits();
// Todo: AVX512 allows gather/scatter, works with strided and random as well
return false;
}
-bool X86TTI::isLegalPredicatedStore(Type *DataType, int Consecutive) const {
- return isLegalPredicatedLoad(DataType, Consecutive);
+bool X86TTI::isLegalMaskedStore(Type *DataType, int Consecutive) const {
+ return isLegalMaskedLoad(DataType, Consecutive);
}
if (Reverse) {
// If the address is consecutive but reversed, then the
- // wide store needs to start at the last vector element.
+ // wide load needs to start at the last vector element.
PartPtr = Builder.CreateGEP(Ptr, Builder.getInt32(-Part * VF));
PartPtr = Builder.CreateGEP(PartPtr, Builder.getInt32(1 - VF));
}
case Instruction::SDiv:
case Instruction::URem:
case Instruction::SRem:
- return false;
+ return false;
}
}
MaxVectorSize = 1;
}
- assert(MaxVectorSize <= 32 && "Did not expect to pack so many elements"
+ assert(MaxVectorSize <= 64 && "Did not expect to pack so many elements"
" into one vector!");
unsigned VF = MaxVectorSize;