soc: sifive: ccache: reduce printing on init

The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index b361b66..17080af 100644 (file)
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -81,20 +81,17 @@ static void setup_sifive_debug(void)
 
 static void ccache_config_read(void)
 {
-       u32 regval, val;
-
-       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
-       val = regval & 0xFF;
-       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
-       val = (regval & 0xFF00) >> 8;
-       pr_info("CCACHE: No. of ways per bank: %d\n", val);
-       val = (regval & 0xFF0000) >> 16;
-       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
-       val = (regval & 0xFF000000) >> 24;
-       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
-
-       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
-       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
+       u32 cfg;
+
+       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+
+       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
+               (cfg & 0xff), (cfg >> 8) & 0xff,
+               BIT_ULL((cfg >> 16) & 0xff),
+               BIT_ULL((cfg >> 24) & 0xff));
+
+       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+       pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg);
 }
 
 static const struct of_device_id sifive_ccache_ids[] = {