arm64: dts: exynos: Add more clocks to Exynos5433 Decon and DeconTV

Add all '1x' clocks to decon and decontv devices. Enabling those clocks
is needed to get proper display on hardware windows no 4 and 5.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I47043438d55591f0202e8ddf3cf4cf86bfa4a9f3

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index a168c5608e81e8b3bc0dc4114b42f31245d0510c..bee00ead0a7b962f2e3dfe3799b2311918e0b2c1 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1381,11 +1381,16 @@
                                <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
                                <&cmu_disp CLK_ACLK_XIU_DECON0X>,
                                <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
+                               <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
+                               <&cmu_disp CLK_ACLK_XIU_DECON1X>,
+                               <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
                                <&cmu_disp CLK_SCLK_DECON_VCLK>,
                                <&cmu_disp CLK_SCLK_DECON_ECLK>;
                        clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
                                "aclk_xiu_decon0x", "pclk_smmu_decon0x",
-                               "sclk_decon_vclk", "sclk_decon_eclk";
+                               "aclk_smmu_decon1x", "aclk_xiu_decon1x",
+                               "pclk_smmu_decon1x", "sclk_decon_vclk",
+                               "sclk_decon_eclk";
                        power-domains = <&pd_disp>;
                        interrupt-names = "fifo", "vsync", "lcd_sys";
                        interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
@@ -1418,11 +1423,16 @@
                                 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
                                 <&cmu_disp CLK_ACLK_XIU_TV0X>,
                                 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+                                <&cmu_disp CLK_ACLK_SMMU_TV1X>,
+                                <&cmu_disp CLK_ACLK_XIU_TV1X>,
+                                <&cmu_disp CLK_PCLK_SMMU_TV1X>,
                                 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
                                 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
                        clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
                                      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
-                                     "sclk_decon_vclk", "sclk_decon_eclk";
+                                     "aclk_smmu_decon1x", "aclk_xiu_decon1x",
+                                     "pclk_smmu_decon1x", "sclk_decon_vclk",
+                                     "sclk_decon_eclk";
                        samsung,disp-sysreg = <&syscon_disp>;
                        power-domains = <&pd_disp>;
                        interrupt-names = "fifo", "vsync", "lcd_sys";