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freedreno/a5xx+: Rename GRAS_CNTL/RB_RENDER_CONTROL0 IJ_LINEAR_* bits.
authorEmma Anholt <emma@anholt.net>
Mon, 20 Sep 2021 21:48:15 +0000 (14:48 -0700)
committerMarge Bot <eric+marge@anholt.net>
Tue, 21 Sep 2021 17:11:42 +0000 (17:11 +0000)
This is what they actually enable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12949>

src/freedreno/.gitlab-ci/reference/fd-clouds.log patch | blob | history
src/freedreno/registers/adreno/a5xx.xml patch | blob | history
src/freedreno/registers/adreno/a6xx.xml patch | blob | history
src/freedreno/vulkan/tu_pipeline.c patch | blob | history
src/gallium/drivers/freedreno/a5xx/fd5_program.c patch | blob | history
src/gallium/drivers/freedreno/a6xx/fd6_program.c patch | blob | history

diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 0126894..296f62b 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -1996,10 +1996,10 @@ t4                                      write VPC_VS_LAYER_CNTL (9104)
                                                VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
 00000000011200d0:                                      0000: 48910401 0000ffff
 t4                                     write GRAS_CNTL (8005)
-                                               GRAS_CNTL: { SIZE | COORD_MASK = 0xf }
+                                               GRAS_CNTL: { IJ_LINEAR_PIXEL | COORD_MASK = 0xf }
 00000000011200d8:                                      0000: 40800501 000003c8
 t4                                     write RB_RENDER_CONTROL0 (8809)
-                                               RB_RENDER_CONTROL0: { SIZE | COORD_MASK = 0xf }
+                                               RB_RENDER_CONTROL0: { IJ_LINEAR_PIXEL | COORD_MASK = 0xf }
                                                RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
 00000000011200e0:                                      0000: 48880902 000003c8 00000000
 t4                                     write RB_SAMPLE_CNTL (8810)
@@ -5174,7 +5174,7 @@ t7                        opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
                        :0,1,17,2
  +     00000080                        GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE }
  +     00000000                        GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
-!+     000003c8                        GRAS_CNTL: { SIZE | COORD_MASK = 0xf }
+!+     000003c8                        GRAS_CNTL: { IJ_LINEAR_PIXEL | COORD_MASK = 0xf }
  +     00057537                        GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 }
  +     44870000                        GRAS_CL_VPORT[0].XOFFSET: 1080.000000
  +     44870000                        GRAS_CL_VPORT[0].XSCALE: 1080.000000
@@ -5195,7 +5195,7 @@ t7                        opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +     059f086f                        GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
  +     00000000                        GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
  +     00000000                        GRAS_SAMPLE_CNTL: { 0 }
-!+     000003c8                        RB_RENDER_CONTROL0: { SIZE | COORD_MASK = 0xf }
+!+     000003c8                        RB_RENDER_CONTROL0: { IJ_LINEAR_PIXEL | COORD_MASK = 0xf }
  +     00000000                        RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
  +     00000000                        RB_FS_OUTPUT_CNTL0: { 0 }
 !+     00000001                        RB_FS_OUTPUT_CNTL1: { MRT = 1 }
diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml
index 55e90f2..87200b1 100644 (file)
--- a/src/freedreno/registers/adreno/a5xx.xml
+++ b/src/freedreno/registers/adreno/a5xx.xml
@@ -1825,14 +1825,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
                <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
                <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
                <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
-               <!--
-               bit 3 set when blob turns on WCOORD.. which also corresponds to
-               register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
-               shader does not use).. possibly providing wcoord in an alternate
-               way??
-               Also, when that happens, VARYING bits are turned on as well.
-                -->
-               <bitfield name="SIZE" pos="3" type="boolean"/>
+               <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+               <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
                <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
        </reg32>
        <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
@@ -1978,14 +1973,9 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
                <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
                <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
                <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
-               <!--
-               bit 3 set when blob turns on WCOORD.. which also corresponds to
-               register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
-               shader does not use).. possibly providing wcoord in an alternate
-               way??
-               Also, when that happens, VARYING bits are turned on as well.
-                -->
-               <bitfield name="SIZE" pos="3" type="boolean"/>
+               <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+               <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
                <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
        </reg32>
        <reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index e02052a..8aea49a 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1565,18 +1565,11 @@ to upconvert to 32b float internally?
        <reg32 offset="0x8005" name="GRAS_CNTL">
                <!-- see also RB_RENDER_CONTROL0 -->
                <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
-               <!-- b1 set for interpolateAtCentroid() -->
                <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
-               <!-- b2 set instead of b0 when running in per-sample mode -->
                <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
-               <!--
-               b3 set for interpolateAt{Offset,Sample}() if not in per-sample
-               mode, and frag_face
-                -->
-               <bitfield name="SIZE" pos="3" type="boolean"/>
-               <bitfield name="UNK4" pos="4" type="boolean"/>
-               <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
-               <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
+               <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+               <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
                <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
        </reg32>
        <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
@@ -1965,18 +1958,11 @@ to upconvert to 32b float internally?
        <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
                <!-- see also GRAS_CNTL -->
                <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
-               <!-- b1 set for interpolateAtCentroid() -->
                <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
-               <!-- b2 set instead of b0 when running in per-sample mode -->
                <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
-               <!--
-               b3 set for interpolateAt{Offset,Sample}() if not in per-sample
-               mode, and frag_face
-                -->
-               <bitfield name="SIZE" pos="3" type="boolean"/>
-               <bitfield name="UNK4" pos="4" type="boolean"/>
-               <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
-               <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
+               <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+               <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
                <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
                <bitfield name="UNK10" pos="10" type="boolean"/>
        </reg32>
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 3216ff1..0813484 100644 (file)
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1438,8 +1438,8 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
          CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
          CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
          CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
-         COND(need_size, A6XX_GRAS_CNTL_SIZE) |
-         COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
+         COND(need_size, A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
+         COND(need_size_persamp, A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
          COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
 
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
@@ -1447,9 +1447,9 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
          CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
          CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
          CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
-         COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
+         COND(need_size, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
          COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
-         COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
+         COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
          COND(fs->fragcoord_compmask != 0,
                            A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
    tu_cs_emit(cs,
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 072d432..531c4e2 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -553,9 +553,9 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        A5XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
                COND(s[FS].v->fragcoord_compmask != 0,
                     A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) |
-                       A5XX_GRAS_CNTL_SIZE) |
-               COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_SIZE) |
-               CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_SIZE));
+                       A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
+               COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
+               CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL));
 
    OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
    OUT_RING(
@@ -566,9 +566,9 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
                  A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
          COND(s[FS].v->fragcoord_compmask != 0,
               A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) |
-                 A5XX_RB_RENDER_CONTROL0_SIZE) |
-         COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_SIZE) |
-         CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_SIZE));
+                 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
+         COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
+         CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL));
    OUT_RING(ring,
             CONDREG(samp_mask_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
                COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS) |
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index e1dae44..c4d9137 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -846,8 +846,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
          CONDREG(ij_regid[IJ_PERSP_CENTROID],
                  A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
          CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
-         COND(need_size, A6XX_GRAS_CNTL_SIZE) |
-         COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
+         COND(need_size, A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
+         COND(need_size_persamp, A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
          COND(fs->fragcoord_compmask != 0,
               A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
 
@@ -860,9 +860,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
                  A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
          CONDREG(ij_regid[IJ_PERSP_SAMPLE],
                  A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
-         COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
+         COND(need_size, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
          COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
-         COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
+         COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
          COND(fs->fragcoord_compmask != 0,
               A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
 
Domain: Graphics System / GL;