mtd: spi-nor: spansion: Consider reserved bits in CFR5 register

CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS}
definition, stop using magic numbers and describe the missing bit fields
in CFR5 register. This is useful for both readability and future possible
addition of Octal STR mode support.

Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash")
Cc: stable@vger.kernel.org
Reported-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Pratyush Yadav <ptyadav@amazon.de>
Tested-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/linux-mtd/20230110164703.83413-1-tudor.ambarus@linaro.org

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index b621cdf..07fe0f6 100644 (file)
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -21,8 +21,13 @@
 #define SPINOR_REG_CYPRESS_CFR3V               0x00800004
 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ          BIT(4) /* Page size. */
 #define SPINOR_REG_CYPRESS_CFR5V               0x00800006
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN    0x3
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS    0
+#define SPINOR_REG_CYPRESS_CFR5_BIT6           BIT(6)
+#define SPINOR_REG_CYPRESS_CFR5_DDR            BIT(1)
+#define SPINOR_REG_CYPRESS_CFR5_OPI            BIT(0)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN                            \
+       (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR |   \
+        SPINOR_REG_CYPRESS_CFR5_OPI)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS    SPINOR_REG_CYPRESS_CFR5_BIT6
 #define SPINOR_OP_CYPRESS_RD_FAST              0xee
 
 /* Cypress SPI NOR flash operations. */