pwm: mtk-disp: Implement atomic API .get_state()

Switch the driver to support the .get_state() method.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
[thierry.reding@gmail.com: add missing linux/bitfield.h include]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 73f8103..c605013 100644 (file)
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -5,6 +5,7 @@
  * Author: YH Huang <yh.huang@mediatek.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -171,8 +172,50 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        return 0;
 }
 
+static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
+                                  struct pwm_device *pwm,
+                                  struct pwm_state *state)
+{
+       struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
+       u64 rate, period, high_width;
+       u32 clk_div, con0, con1;
+       int err;
+
+       err = clk_prepare_enable(mdp->clk_main);
+       if (err < 0) {
+               dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
+               return;
+       }
+
+       err = clk_prepare_enable(mdp->clk_mm);
+       if (err < 0) {
+               dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
+               clk_disable_unprepare(mdp->clk_main);
+               return;
+       }
+
+       rate = clk_get_rate(mdp->clk_main);
+       con0 = readl(mdp->base + mdp->data->con0);
+       con1 = readl(mdp->base + mdp->data->con1);
+       state->enabled = !!(con0 & BIT(0));
+       clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
+       period = FIELD_GET(PWM_PERIOD_MASK, con1);
+       /*
+        * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
+        * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
+        */
+       state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
+       high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
+       state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
+                                              rate);
+       state->polarity = PWM_POLARITY_NORMAL;
+       clk_disable_unprepare(mdp->clk_mm);
+       clk_disable_unprepare(mdp->clk_main);
+}
+
 static const struct pwm_ops mtk_disp_pwm_ops = {
        .apply = mtk_disp_pwm_apply,
+       .get_state = mtk_disp_pwm_get_state,
        .owner = THIS_MODULE,
 };