Fix cfa offset for saved registers in PPC sqrt implementations.

diff --git a/ChangeLog b/ChangeLog
index 4ef72fc..3e1f365 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,11 @@
+2009-06-24  Andreas Schwab  <aschwab@redhat.com>
+
+       * sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S: Fix cfa offset
+       for saved registers.
+       * sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S: Likewise.
+       * sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S: Likewise.
+       * sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S: Likewise.
+
 2009-06-23  Andreas Schwab  <aschwab@redhat.com>
 
        * time/tzfile.c (__tzfile_read): Don't use an empty TZ string.

diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
index 6aef4e3..95a0b39 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
@@ -60,8 +60,8 @@ EALIGN (__sqrt, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1

diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
index e5b8b9d..c315551 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
@@ -60,8 +60,8 @@ EALIGN (__sqrtf, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1

diff --git a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S
index 925930b..105b591 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S
+++ b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S
@@ -60,8 +60,8 @@ EALIGN (__sqrt, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1

diff --git a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S
index 891e69c..14bc0a2 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S
+++ b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S
@@ -60,8 +60,8 @@ EALIGN (__sqrtf, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1