assert(layout->set[s].dynamic_offset_start < MAX_DYNAMIC_BUFFERS);
if (layout->set[s].layout->dynamic_offset_count > 0 &&
- (push->desc_sets[s] & ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK) != layout->set[s].dynamic_offset_start) {
- push->desc_sets[s] &= ~ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK;
- push->desc_sets[s] |= (layout->set[s].dynamic_offset_start &
- ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
+ (push->desc_offsets[s] & ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK) != layout->set[s].dynamic_offset_start) {
+ push->desc_offsets[s] &= ~ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK;
+ push->desc_offsets[s] |= (layout->set[s].dynamic_offset_start &
+ ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
modified = true;
}
}
if (update_desc_sets) {
struct anv_push_constants *push = &pipe_state->push_constants;
- struct anv_address addr = anv_descriptor_set_address(set);
- push->desc_sets[set_index] &= ~ANV_DESCRIPTOR_SET_ADDRESS_MASK;
- push->desc_sets[set_index] |= (anv_address_physical(addr) &
- ANV_DESCRIPTOR_SET_ADDRESS_MASK);
+ struct anv_address set_addr = anv_descriptor_set_address(set);
+ uint64_t addr = anv_address_physical(set_addr);
+ uint32_t offset = addr & 0xffffffff;
+ assert((offset & ~ANV_DESCRIPTOR_SET_OFFSET_MASK) == 0);
+ push->desc_offsets[set_index] &= ~ANV_DESCRIPTOR_SET_OFFSET_MASK;
+ push->desc_offsets[set_index] |= offset;
- if (addr.bo) {
+ if (set_addr.bo) {
anv_reloc_list_add_bo(cmd_buffer->batch.relocs,
cmd_buffer->batch.alloc,
- addr.bo);
+ set_addr.bo);
}
}
case nir_intrinsic_load_desc_set_address_intel:
case nir_intrinsic_load_desc_set_dynamic_index_intel: {
- unsigned base = offsetof(struct anv_push_constants, desc_sets);
+ unsigned base = offsetof(struct anv_push_constants, desc_offsets);
push_start = MIN2(push_start, base);
push_end = MAX2(push_end, base +
- sizeof_field(struct anv_push_constants, desc_sets));
+ sizeof_field(struct anv_push_constants, desc_offsets));
break;
}
case nir_intrinsic_load_desc_set_address_intel: {
b->cursor = nir_before_instr(&intrin->instr);
- nir_ssa_def *pc_load = nir_load_uniform(b, 1, 64,
- nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint64_t)),
- .base = offsetof(struct anv_push_constants, desc_sets),
- .range = sizeof_field(struct anv_push_constants, desc_sets),
- .dest_type = nir_type_uint64);
- pc_load = nir_iand_imm(b, pc_load, ANV_DESCRIPTOR_SET_ADDRESS_MASK);
- nir_ssa_def_rewrite_uses(&intrin->dest.ssa, pc_load);
+ nir_ssa_def *pc_load = nir_load_uniform(b, 1, 32,
+ nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
+ .base = offsetof(struct anv_push_constants, desc_offsets),
+ .range = sizeof_field(struct anv_push_constants, desc_offsets),
+ .dest_type = nir_type_uint32);
+ pc_load = nir_iand_imm(b, pc_load, ANV_DESCRIPTOR_SET_OFFSET_MASK);
+ nir_ssa_def *desc_addr =
+ nir_pack_64_2x32_split(
+ b, pc_load,
+ nir_load_reloc_const_intel(
+ b, BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH));
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc_addr);
break;
}
case nir_intrinsic_load_desc_set_dynamic_index_intel: {
b->cursor = nir_before_instr(&intrin->instr);
- nir_ssa_def *pc_load = nir_load_uniform(b, 1, 64,
- nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint64_t)),
- .base = offsetof(struct anv_push_constants, desc_sets),
- .range = sizeof_field(struct anv_push_constants, desc_sets),
- .dest_type = nir_type_uint64);
- pc_load = nir_i2i32(
- b,
- nir_iand_imm(
- b, pc_load, ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK));
+ nir_ssa_def *pc_load = nir_load_uniform(b, 1, 32,
+ nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
+ .base = offsetof(struct anv_push_constants, desc_offsets),
+ .range = sizeof_field(struct anv_push_constants, desc_offsets),
+ .dest_type = nir_type_uint32);
+ pc_load = nir_iand_imm(
+ b, pc_load, ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, pc_load);
break;
}
prog_data_in->const_data_offset;
int rv_count = 0;
- struct brw_shader_reloc_value reloc_values[5];
+ struct brw_shader_reloc_value reloc_values[6];
+ assert((device->physical->va.instruction_state_pool.addr & 0xffffffff) == 0);
+ reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
+ .id = BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH,
+ .value = device->physical->indirect_descriptors ?
+ (device->physical->va.descriptor_pool.addr >> 32) :
+ (device->physical->va.binding_table_pool.addr >> 32),
+ };
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW,
.value = shader_data_addr,