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Update ACL (#2301)
author장지섭/동작제어Lab(SR)/Engineer/삼성전자 <jiseob.jang@samsung.com>
Thu, 16 Aug 2018 02:26:58 +0000 (11:26 +0900)
committer오형석/동작제어Lab(SR)/Staff Engineer/삼성전자 <hseok82.oh@samsung.com>
Thu, 16 Aug 2018 02:26:58 +0000 (11:26 +0900)
- Enable QASYMM8 in the CLArithmeticAdditionKernel.
- Extend the range in which StridedSlice is supported for CPU.
- Bugfix of subtensor validation.
- Unify the order of input data in StridedSliceCPU.

Signed-off-by: jiseob.jang <jiseob.jang@samsung.com>
externals/acl patch | blob | history

diff --git a/externals/acl b/externals/acl
index ffb262b..b29bc9e 160000 (submodule)
--- a/externals/acl
+++ b/externals/acl
@@ -1 +1 @@
-Subproject commit ffb262b0d0a159289c5437e55d92876f6da1dfdb
+Subproject commit b29bc9ed09561c93f5cffb61e2e74222cd4a4542
Domain: Machine Learning / ML Framework;